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| author | Craig Topper <craig.topper@intel.com> | 2018-12-03 18:26:27 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-12-03 18:26:27 +0000 |
| commit | 5440b63fa8a1aa73e7422239919d64b21df93f6d (patch) | |
| tree | 4d74c923d3771045451592e9a59696d9f7788252 /lldb/packages/Python/lldbsuite/test/expression_command/call-function/TestCallStdStringFunction.py | |
| parent | e35b01f8ea75b353fb6541e3d58e056f497b1cf2 (diff) | |
| download | bcm5719-llvm-5440b63fa8a1aa73e7422239919d64b21df93f6d.tar.gz bcm5719-llvm-5440b63fa8a1aa73e7422239919d64b21df93f6d.zip | |
[X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS.
Summary:
We need to unpackl and unpackh the operands to use two vXi16 multiplies. Previously it looks like the low unpack would get constant folded at least in the 128-bit case after shuffle lowering turned the unpackl into ZERO_EXTEND_VECTOR_INREG and X86 custom DAG combined it. The same doesn't happen for the high half. So we'd load a constant and then shuffle it. But the low half would just be loaded and used by the multiply directly.
After this patch we now end up with a constant pool entry for the low and high unpacks separately with no shuffle operations.
This is a step towards removing custom constant folding for ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG in the X86 backend.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D55165
llvm-svn: 348159
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/call-function/TestCallStdStringFunction.py')
0 files changed, 0 insertions, 0 deletions
