diff options
| author | Jason Molenda <jmolenda@apple.com> | 2019-10-16 19:14:49 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 2019-10-16 19:14:49 +0000 |
| commit | 7dd7a3607596a51044b8706ebf6df2e613ce1e9b (patch) | |
| tree | ceaacaa39ab7238f81442a520fc67f7c17b7294f /lldb/packages/Python/lldbsuite/test/commands/register | |
| parent | 930ada91ce8ff9715e2ca7309bc946dbb9162dfb (diff) | |
| download | bcm5719-llvm-7dd7a3607596a51044b8706ebf6df2e613ce1e9b.tar.gz bcm5719-llvm-7dd7a3607596a51044b8706ebf6df2e613ce1e9b.zip | |
Add arm64_32 support to lldb, an ILP32 codegen
that runs on arm64 ISA targets, specifically
Apple watches.
Differential Revision: https://reviews.llvm.org/D68858
llvm-svn: 375032
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/commands/register')
| -rw-r--r-- | lldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py b/lldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py index 44e02335dab..f9b187bc2b4 100644 --- a/lldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py +++ b/lldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py @@ -44,7 +44,7 @@ class RegisterCommandsTestCase(TestBase): self.runCmd("register read xmm0") self.runCmd("register read ymm15") # may be available self.runCmd("register read bnd0") # may be available - elif self.getArchitecture() in ['arm', 'armv7', 'armv7k', 'arm64']: + elif self.getArchitecture() in ['arm', 'armv7', 'armv7k', 'arm64', 'arm64e', 'arm64_32']: self.runCmd("register read s0") self.runCmd("register read q15") # may be available @@ -89,7 +89,7 @@ class RegisterCommandsTestCase(TestBase): if self.getArchitecture() in ['amd64', 'i386', 'x86_64']: gpr = "eax" vector = "xmm0" - elif self.getArchitecture() in ['arm64', 'aarch64']: + elif self.getArchitecture() in ['arm64', 'aarch64', 'arm64e', 'arm64_32']: gpr = "w0" vector = "v0" elif self.getArchitecture() in ['arm', 'armv7', 'armv7k']: @@ -335,7 +335,7 @@ class RegisterCommandsTestCase(TestBase): ("xmm15", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", False)) - elif self.getArchitecture() in ['arm64', 'aarch64']: + elif self.getArchitecture() in ['arm64', 'aarch64', 'arm64e', 'arm64_32']: reg_list = [ # reg value # must-have |
