diff options
| author | David Green <david.green@arm.com> | 2019-09-03 11:30:54 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-09-03 11:30:54 +0000 |
| commit | 2f3574c16894f87dd797b8962babb4a766503279 (patch) | |
| tree | fbdd66d4cc404fa9e2c639164cdb50cead1c64e3 /lldb/packages/Python/lldbsuite/test/commands/command/script/welcome.py | |
| parent | 92b2be1e92329eabf78ae305b8c1c40c6b3a681d (diff) | |
| download | bcm5719-llvm-2f3574c16894f87dd797b8962babb4a766503279.tar.gz bcm5719-llvm-2f3574c16894f87dd797b8962babb4a766503279.zip | |
[ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
The code here seems to date back to r134705, when tablegen lowering was first
being added. I don't believe that we need to include CPSR implicit operands on
the MCInst. This now works more like other backends (like AArch64), where all
implicit registers are skipped.
This allows the AliasInst for CSEL's to match correctly, as can be seen in the
test changes.
Differential revision: https://reviews.llvm.org/D66703
llvm-svn: 370745
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/commands/command/script/welcome.py')
0 files changed, 0 insertions, 0 deletions
