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author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-03-07 13:28:29 +0000 |
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committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-03-07 13:28:29 +0000 |
commit | 3d3120dc9ab5769805b259831e6cffdcc9adb019 (patch) | |
tree | fb31afffc9dbacf133d0c6632ce2d3665fcd8974 /lldb/packages/Python/lldbsuite/support/encoded_file.py | |
parent | 16d98c206b75080d5057ec639c92a460c8be9456 (diff) | |
download | bcm5719-llvm-3d3120dc9ab5769805b259831e6cffdcc9adb019.tar.gz bcm5719-llvm-3d3120dc9ab5769805b259831e6cffdcc9adb019.zip |
[MIPS GlobalISel] Fix mul operands
Unsigned mul high for MIPS32 is selected into two PseudoInstructions:
PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for
some of its operands. Registers in this class have appropriate hi and lo
register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc.
mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td.
In functions where mul and PseudoMULTu are present fastRegisterAllocator
will "run out of registers during register allocation" because
'calcSpillCost' for $ac0 will return spillImpossible because subregisters
$lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is
to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction.
Differential Revision: https://reviews.llvm.org/D58715
llvm-svn: 355594
Diffstat (limited to 'lldb/packages/Python/lldbsuite/support/encoded_file.py')
0 files changed, 0 insertions, 0 deletions