[OR1K] Add the EPCR special-purpose register to register state.

This makes it possible to unwind hardware exception stack frames,
which necessarily save every register and so need an extra column
for storing the return address. CFI for the exception handler could
then look as follows:

.globl exception_vector
exception_vector:
    .cfi_startproc
    .cfi_signal_frame
    .cfi_return_column 32
    l.addi  r1, r1, -0x100
    .cfi_def_cfa_offset 0x100
    l.sw    0x00(r1), r2
    .cfi_offset 2, 0x00-0x100
    l.sw    0x04(r1), r3
    .cfi_offset 3, 0x04-0x100
    l.sw    0x08(r1), r4
    .cfi_offset 4, 0x08-0x100
    l.mfspr r3, r0, SPR_EPCR_BASE
    l.sw    0x78(r1), r3
    .cfi_offset 32, 0x78-0x100
    l.jal   exception_handler
     l.nop
    l.lwz   r2, 0x00(r1)
    l.lwz   r3, 0x04(r1)
    l.lwz   r4, 0x08(r1)
    l.jr    r9
     l.nop
    .cfi_endproc

This register could, of course, also be accessed by the trace
callback or personality function, if so desired.

llvm-svn: 332513

2 files changed, 2 insertions, 1 deletions

diff --git a/libunwind/include/__libunwind_config.h b/libunwind/include/__libunwind_config.h
index 584c57029fa..5464e367060 100644
--- a/libunwind/include/__libunwind_config.h
+++ b/libunwind/include/__libunwind_config.h
@@ -21,7 +21,7 @@
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64     116
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64     95
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM       287
-#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K      31
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K      32
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS      65
 
 #if defined(_LIBUNWIND_IS_NATIVE_ONLY)
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
index 8e3d3fe9af2..97d2b82290c 100644
--- a/libunwind/include/libunwind.h
+++ b/libunwind/include/libunwind.h
@@ -745,6 +745,7 @@ enum {
   UNW_OR1K_R29 = 29,
   UNW_OR1K_R30 = 30,
   UNW_OR1K_R31 = 31,
+  UNW_OR1K_EPCR = 32,
 };
 
 // MIPS registers