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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-21 20:45:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-21 20:45:36 +0000 |
| commit | b34afa311d25f1eda0bad3415e880bc18e3072b1 (patch) | |
| tree | 67e13994e96cc694006d2ee8d91046cd77275782 /libcxx/test/std/utilities/function.objects/bitwise.operations/bit_and.pass.cpp | |
| parent | 6d69fec64516de1e64882aa4452f544c7b890357 (diff) | |
| download | bcm5719-llvm-b34afa311d25f1eda0bad3415e880bc18e3072b1.tar.gz bcm5719-llvm-b34afa311d25f1eda0bad3415e880bc18e3072b1.zip | |
GlobalISel: Fix RegBankSelect for REG_SEQUENCE
The AArch64 test was broken since the result register already had a
set register class, so this test was a no-op. The mapping verify call
would fail because the result size is not the same as the inputs like
in a copy or phi.
The AMDGPU testcases are half broken and introduce illegal VGPR->SGPR
copies which need much more work to handle correctly (same for phis),
but add them as a baseline.
llvm-svn: 356713
Diffstat (limited to 'libcxx/test/std/utilities/function.objects/bitwise.operations/bit_and.pass.cpp')
0 files changed, 0 insertions, 0 deletions
