Fix and re-enable R600 vload/vstore assembly

The assembly optimizations were making unsafe assumptions about which address
spaces had which identifiers.

Also, fix vload/vstore with 64-bit pointers. This was broken previously on
Radeon SI.

This version still only has assembly versions of int/uint 2/4/8/16 for global
loads and stores on R600, but it does it in a way that would be very easily
extended to private/local/constant and could also be handled easily on other
architectures.

v2: 1) Leave v[load|store]_impl.ll in generic/lib
    2) Remove vload_if.ll and vstore_if.ll interfaces
    3) Fix address+offset calculations
    3) Remove offset from assembly arg list
llvm-svn: 186416

1 files changed, 15 insertions, 26 deletions

diff --git a/libclc/generic/lib/shared/vstore_impl.ll b/libclc/generic/lib/shared/vstore_impl.ll
index 3baab5eb99a..388bce2d097 100644
--- a/libclc/generic/lib/shared/vstore_impl.ll
+++ b/libclc/generic/lib/shared/vstore_impl.ll
@@ -1,46 +1,35 @@
 ; This provides optimized implementations of vstore4/8/16 for 32-bit int/uint
 
-define void @__clc_vstore2_impl_i32__global(<2 x i32> %vec, i32 %offset,  i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
-  %1 = ptrtoint i32 addrspace(1)* %addr to i32
-  %2 = add i32 %1, %offset
-  %3 = inttoptr i32 %2 to <2 x i32> addrspace(1)*
-  store <2 x i32> %vec, <2 x i32> addrspace(1)* %3, align 4, !tbaa !3
+define void @__clc_vstore2_i32__addr1(<2 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
+  %1 = bitcast i32 addrspace(1)* %addr to <2 x i32> addrspace(1)*
+  store <2 x i32> %vec, <2 x i32> addrspace(1)* %1, align 4, !tbaa !3
   ret void
 }
 
-define void @__clc_vstore3_impl_i32__global(<3 x i32> %vec, i32 %offset,  i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
-  %1 = ptrtoint i32 addrspace(1)* %addr to i32
-  %2 = add i32 %1, %offset
-  %3 = inttoptr i32 %2 to <3 x i32> addrspace(1)*
-  store <3 x i32> %vec, <3 x i32> addrspace(1)* %3, align 4, !tbaa !3
+define void @__clc_vstore3_i32__addr1(<3 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
+  %1 = bitcast i32 addrspace(1)* %addr to <3 x i32> addrspace(1)*
+  store <3 x i32> %vec, <3 x i32> addrspace(1)* %1, align 4, !tbaa !3
   ret void
 }
 
-define void @__clc_vstore4_impl_i32__global(<4 x i32> %vec, i32 %offset,  i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
-  %1 = ptrtoint i32 addrspace(1)* %addr to i32
-  %2 = add i32 %1, %offset
-  %3 = inttoptr i32 %2 to <4 x i32> addrspace(1)*
-  store <4 x i32> %vec, <4 x i32> addrspace(1)* %3, align 4, !tbaa !3
+define void @__clc_vstore4_i32__addr1(<4 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
+  %1 = bitcast i32 addrspace(1)* %addr to <4 x i32> addrspace(1)*
+  store <4 x i32> %vec, <4 x i32> addrspace(1)* %1, align 4, !tbaa !3
   ret void
 }
 
-define void @__clc_vstore8_impl_i32__global(<8 x i32> %vec, i32 %offset,  i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
-  %1 = ptrtoint i32 addrspace(1)* %addr to i32
-  %2 = add i32 %1, %offset
-  %3 = inttoptr i32 %2 to <8 x i32> addrspace(1)*
-  store <8 x i32> %vec, <8 x i32> addrspace(1)* %3, align 4, !tbaa !3
+define void @__clc_vstore8_i32__addr1(<8 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
+  %1 = bitcast i32 addrspace(1)* %addr to <8 x i32> addrspace(1)*
+  store <8 x i32> %vec, <8 x i32> addrspace(1)* %1, align 4, !tbaa !3
   ret void
 }
 
-define void @__clc_vstore16_impl_i32__global(<16 x i32> %vec, i32 %offset,  i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
-  %1 = ptrtoint i32 addrspace(1)* %addr to i32
-  %2 = add i32 %1, %offset
-  %3 = inttoptr i32 %2 to <16 x i32> addrspace(1)*
-  store <16 x i32> %vec, <16 x i32> addrspace(1)* %3, align 4, !tbaa !3
+define void @__clc_vstore16_i32__addr1(<16 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
+  %1 = bitcast i32 addrspace(1)* %addr to <16 x i32> addrspace(1)*
+  store <16 x i32> %vec, <16 x i32> addrspace(1)* %1, align 4, !tbaa !3
   ret void
 }
 
-
 !1 = metadata !{metadata !"char", metadata !5}
 !2 = metadata !{metadata !"short", metadata !5}
 !3 = metadata !{metadata !"int", metadata !5}