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| author | Martin Storsjo <martin@martin.st> | 2018-01-24 10:14:52 +0000 |
|---|---|---|
| committer | Martin Storsjo <martin@martin.st> | 2018-01-24 10:14:52 +0000 |
| commit | 09bc73d11f86f7127ddfac1bd5d49e1ed596092d (patch) | |
| tree | 845e6bf90d71395b4525a4026c023c049d8620f6 /compiler-rt/lib/builtins | |
| parent | 50acecf2aba22d676a5ac0c8b2654912e0feecb8 (diff) | |
| download | bcm5719-llvm-09bc73d11f86f7127ddfac1bd5d49e1ed596092d.tar.gz bcm5719-llvm-09bc73d11f86f7127ddfac1bd5d49e1ed596092d.zip | |
[builtins] Align addresses to cache lines in __clear_cache for aarch64
This makes sure that the last cache line gets invalidated properly.
This matches the example code at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html,
and also matches what libgcc does.
Differential Revision: https://reviews.llvm.org/D42196
llvm-svn: 323315
Diffstat (limited to 'compiler-rt/lib/builtins')
| -rw-r--r-- | compiler-rt/lib/builtins/clear_cache.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c index f92ef1cd48e..9dcab344ad1 100644 --- a/compiler-rt/lib/builtins/clear_cache.c +++ b/compiler-rt/lib/builtins/clear_cache.c @@ -163,12 +163,14 @@ void __clear_cache(void *start, void *end) { * uintptr_t in case this runs in an IPL32 environment. */ const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); - for (addr = xstart; addr < xend; addr += dcache_line_size) + for (addr = xstart & ~(dcache_line_size - 1); addr < xend; + addr += dcache_line_size) __asm __volatile("dc cvau, %0" :: "r"(addr)); __asm __volatile("dsb ish"); const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); - for (addr = xstart; addr < xend; addr += icache_line_size) + for (addr = xstart & ~(icache_line_size - 1); addr < xend; + addr += icache_line_size) __asm __volatile("ic ivau, %0" :: "r"(addr)); __asm __volatile("isb sy"); #elif defined (__powerpc64__) |
