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| author | Martin Storsjo <martin@martin.st> | 2018-01-19 07:34:46 +0000 |
|---|---|---|
| committer | Martin Storsjo <martin@martin.st> | 2018-01-19 07:34:46 +0000 |
| commit | fe011a6ed95c111c5c9e9915dc7176ef99f5f66a (patch) | |
| tree | f2ae643793e1a9030091fd773456772d221fdf16 /compiler-rt/lib/builtins/clear_cache.c | |
| parent | 4a7c8e7aa2e9845652703141b240f9179f1f9980 (diff) | |
| download | bcm5719-llvm-fe011a6ed95c111c5c9e9915dc7176ef99f5f66a.tar.gz bcm5719-llvm-fe011a6ed95c111c5c9e9915dc7176ef99f5f66a.zip | |
[builtins] Use FlushInstructionCache on windows on aarch64 as well
Generalize this handling to a separate toplevel ifdef (since any
windows case should use the same function), instead of indenting
the aarch64 case one step further.
Differential Revision: https://reviews.llvm.org/D42197
llvm-svn: 322928
Diffstat (limited to 'compiler-rt/lib/builtins/clear_cache.c')
| -rw-r--r-- | compiler-rt/lib/builtins/clear_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c index 4a01cb46d4a..3614bc9c4d4 100644 --- a/compiler-rt/lib/builtins/clear_cache.c +++ b/compiler-rt/lib/builtins/clear_cache.c @@ -96,6 +96,8 @@ void __clear_cache(void *start, void *end) { * Intel processors have a unified instruction and data cache * so there is nothing to do */ +#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__)) + FlushInstructionCache(GetCurrentProcess(), start, end - start); #elif defined(__arm__) && !defined(__APPLE__) #if defined(__FreeBSD__) || defined(__NetBSD__) struct arm_sync_icache_args arg; @@ -123,8 +125,6 @@ void __clear_cache(void *start, void *end) { : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags)); assert(start_reg == 0 && "Cache flush syscall failed."); - #elif defined(_WIN32) - FlushInstructionCache(GetCurrentProcess(), start, end - start); #else compilerrt_abort(); #endif |
