[builtins] Use single line C++/C99 comment style

Use the uniform single line C++/99 style for code comments.

This is part of the cleanup proposed in "[RFC] compiler-rt builtins
cleanup and refactoring".

Differential Revision: https://reviews.llvm.org/D60352

llvm-svn: 359411

1 files changed, 45 insertions, 56 deletions

diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
index 8e4f35ea916..76dc1968cc7 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -1,11 +1,10 @@
-/* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- * ===----------------------------------------------------------------------===
- */
+//===-- clear_cache.c - Implement __clear_cache ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
 
 #include "int_lib.h"
 #include <assert.h>
@@ -16,8 +15,8 @@
 #endif
 
 #if defined(_WIN32)
-/* Forward declare Win32 APIs since the GCC mode driver does not handle the
-   newer SDKs as well as needed.  */
+// Forward declare Win32 APIs since the GCC mode driver does not handle the
+// newer SDKs as well as needed.
 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
                                uintptr_t dwSize);
 uintptr_t GetCurrentProcess(void);
@@ -42,42 +41,40 @@ uintptr_t GetCurrentProcess(void);
 #include <sys/syscall.h>
 #include <unistd.h>
 #if defined(__ANDROID__) && defined(__LP64__)
-/*
- * clear_mips_cache - Invalidates instruction cache for Mips.
- */
+// clear_mips_cache - Invalidates instruction cache for Mips.
 static void clear_mips_cache(const void *Addr, size_t Size) {
   __asm__ volatile(
       ".set push\n"
       ".set noreorder\n"
       ".set noat\n"
-      "beq %[Size], $zero, 20f\n" /* If size == 0, branch around. */
+      "beq %[Size], $zero, 20f\n" // If size == 0, branch around.
       "nop\n"
-      "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */
-      "rdhwr $v0, $1\n"                   /* Get step size for SYNCI.
-                                             $1 is $HW_SYNCI_Step */
-      "beq $v0, $zero, 20f\n"             /* If no caches require
-                                             synchronization, branch
-                                             around. */
+      "daddu %[Size], %[Addr], %[Size]\n" // Calculate end address + 1
+      "rdhwr $v0, $1\n"                   // Get step size for SYNCI.
+                                          // $1 is $HW_SYNCI_Step
+      "beq $v0, $zero, 20f\n"             // If no caches require
+                                          // synchronization, branch
+                                          // around.
       "nop\n"
       "10:\n"
-      "synci 0(%[Addr])\n"            /* Synchronize all caches around
-                                         address. */
-      "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */
-      "sltu $at, %[Addr], %[Size]\n"  /* Compare current with end
-                                         address. */
-      "bne $at, $zero, 10b\n"         /* Branch if more to do. */
+      "synci 0(%[Addr])\n"            // Synchronize all caches around
+                                      // address.
+      "daddu %[Addr], %[Addr], $v0\n" // Add step size.
+      "sltu $at, %[Addr], %[Size]\n"  // Compare current with end
+                                      // address.
+      "bne $at, $zero, 10b\n"         // Branch if more to do.
       "nop\n"
-      "sync\n" /* Clear memory hazards. */
+      "sync\n" // Clear memory hazards.
       "20:\n"
       "bal 30f\n"
       "nop\n"
       "30:\n"
-      "daddiu $ra, $ra, 12\n" /* $ra has a value of $pc here.
-                                 Add offset of 12 to point to the
-                                 instruction after the last nop.
-                               */
-      "jr.hb $ra\n"           /* Return, clearing instruction
-                                 hazards. */
+      "daddiu $ra, $ra, 12\n" // $ra has a value of $pc here.
+                              // Add offset of 12 to point to the
+                              // instruction after the last nop.
+                              //
+      "jr.hb $ra\n"           // Return, clearing instruction
+                              // hazards.
       "nop\n"
       ".set pop\n"
       : [ Addr ] "+r"(Addr), [ Size ] "+r"(Size)::"at", "ra", "v0", "memory");
@@ -85,19 +82,15 @@ static void clear_mips_cache(const void *Addr, size_t Size) {
 #endif
 #endif
 
-/*
- * The compiler generates calls to __clear_cache() when creating
- * trampoline functions on the stack for use with nested functions.
- * It is expected to invalidate the instruction cache for the
- * specified range.
- */
+// The compiler generates calls to __clear_cache() when creating
+// trampoline functions on the stack for use with nested functions.
+// It is expected to invalidate the instruction cache for the
+// specified range.
 
 void __clear_cache(void *start, void *end) {
 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
-/*
- * Intel processors have a unified instruction and data cache
- * so there is nothing to do
- */
+// Intel processors have a unified instruction and data cache
+// so there is nothing to do
 #elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
   FlushInstructionCache(GetCurrentProcess(), start, end - start);
 #elif defined(__arm__) && !defined(__APPLE__)
@@ -109,14 +102,12 @@ void __clear_cache(void *start, void *end) {
 
   sysarch(ARM_SYNC_ICACHE, &arg);
 #elif defined(__linux__)
-/*
- * We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
- * it also brought many other unused defines, as well as a dependency on
- * kernel headers to be installed.
- *
- * This value is stable at least since Linux 3.13 and should remain so for
- * compatibility reasons, warranting it's re-definition here.
- */
+// We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
+// it also brought many other unused defines, as well as a dependency on
+// kernel headers to be installed.
+//
+// This value is stable at least since Linux 3.13 and should remain so for
+// compatibility reasons, warranting it's re-definition here.
 #define __ARM_NR_cacheflush 0x0f0002
   register int start_reg __asm("r0") = (int)(intptr_t)start;
   const register int end_reg __asm("r1") = (int)(intptr_t)end;
@@ -154,10 +145,8 @@ void __clear_cache(void *start, void *end) {
   uint64_t ctr_el0;
   __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
 
-  /*
-   * dc & ic instructions must use 64bit registers so we don't use
-   * uintptr_t in case this runs in an IPL32 environment.
-   */
+  // dc & ic instructions must use 64bit registers so we don't use
+  // uintptr_t in case this runs in an IPL32 environment.
   const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
   for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
        addr += dcache_line_size)
@@ -186,7 +175,7 @@ void __clear_cache(void *start, void *end) {
   __asm__ volatile("isync");
 #else
 #if __APPLE__
-  /* On Darwin, sys_icache_invalidate() provides this functionality */
+  // On Darwin, sys_icache_invalidate() provides this functionality
   sys_icache_invalidate(start, end - start);
 #else
   compilerrt_abort();