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| author | Moritz Roth <moritz.roth@arm.com> | 2014-09-16 16:25:07 +0000 |
|---|---|---|
| committer | Moritz Roth <moritz.roth@arm.com> | 2014-09-16 16:25:07 +0000 |
| commit | eef9f4dc74d081393eaca26186b3c12c16d24b61 (patch) | |
| tree | 7e6d183c3b3fe0f13c90fc4c42ebcb94109d2db6 /clang | |
| parent | 0085300a240208b0089eddf7859b5654a3ab3184 (diff) | |
| download | bcm5719-llvm-eef9f4dc74d081393eaca26186b3c12c16d24b61.tar.gz bcm5719-llvm-eef9f4dc74d081393eaca26186b3c12c16d24b61.zip | |
ARM load/store optimizer: Don't materialize a new base register with
ADDS/SUBS unless it's safe to clobber the condition flags.
If the merged instructions are in a range where the CPSR is live,
e.g. between a CMP -> Bcc, we can't safely materialize a new base
register.
This problem is quite rare, I couldn't come up with a test case and I've
never actually seen this happen in the tests I'm running - there is a
potential trigger for this in LNT/oggenc (spills being inserted between
a CMP/Bcc), but at the moment this isn't being merged. I'll try to
reduce that into a small test case once I've committed my upcoming patch
to make merging less conservative.
llvm-svn: 217881
Diffstat (limited to 'clang')
0 files changed, 0 insertions, 0 deletions
