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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-02 15:41:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-02 15:41:42 +0000 |
| commit | eba61071d7bac3933af19064a27b56c02f51be27 (patch) | |
| tree | 956f9089a9c04be01ac3512ed0f5bd3fd5055841 /clang/unittests/Format/FormatTest.cpp | |
| parent | 9a6b29540ebc5e82551da50a3c63e220887c1445 (diff) | |
| download | bcm5719-llvm-eba61071d7bac3933af19064a27b56c02f51be27.tar.gz bcm5719-llvm-eba61071d7bac3933af19064a27b56c02f51be27.zip | |
R600/SI: Only create one instruction when spilling/restoring register v3
The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.
v2:
- Fix calculation of lane index
- Extend VGPR liveness to end of program.
v3:
- Use SIMM16 field of S_NOP to specify multiple NOPs.
https://bugs.freedesktop.org/show_bug.cgi?id=75005
llvm-svn: 207843
Diffstat (limited to 'clang/unittests/Format/FormatTest.cpp')
0 files changed, 0 insertions, 0 deletions
