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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-18 16:02:23 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-18 16:02:23 +0000 |
| commit | e9effe9744bda67051ab2ff0a76ecc9e99488efa (patch) | |
| tree | d27c7062ef8bddd7e9fcc7b91d4788800bbbc2d4 /clang/tools/scan-view/share/Reporter.py | |
| parent | 0a5e4eb77669253af615d4b32567897bba23642f (diff) | |
| download | bcm5719-llvm-e9effe9744bda67051ab2ff0a76ecc9e99488efa.tar.gz bcm5719-llvm-e9effe9744bda67051ab2ff0a76ecc9e99488efa.zip | |
[X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering for splat rotation amounts
Noticed by @spatel on D55747 - we get much better codegen if we use the regular shift expansion.
llvm-svn: 349500
Diffstat (limited to 'clang/tools/scan-view/share/Reporter.py')
0 files changed, 0 insertions, 0 deletions
