[PPC] revert r287795

A test that passed locally is failing on one of the build bots.

llvm-svn: 287796

4 files changed, 8 insertions, 210 deletions

diff --git a/clang/test/CodeGen/builtins-ppc-altivec.c b/clang/test/CodeGen/builtins-ppc-altivec.c
index 3b75cb49c3f..7aa52a6414d 100644
--- a/clang/test/CodeGen/builtins-ppc-altivec.c
+++ b/clang/test/CodeGen/builtins-ppc-altivec.c
@@ -89,43 +89,6 @@ void test1() {
 // CHECK-NOALTIVEC: error: use of undeclared identifier 'vf'
 // CHECK-NOALTIVEC: vf = vec_abs(vf) 
 
-  vsc = vec_nabs(vsc);
-// CHECK: sub <16 x i8> zeroinitializer
-// CHECK: @llvm.ppc.altivec.vminsb
-// CHECK-LE: sub <16 x i8> zeroinitializer
-// CHECK-LE: @llvm.ppc.altivec.vminsb
-
-  vs = vec_nabs(vs);
-// CHECK: sub <8 x i16> zeroinitializer
-// CHECK: @llvm.ppc.altivec.vminsh
-// CHECK-LE: sub <8 x i16> zeroinitializer
-// CHECK-LE: @llvm.ppc.altivec.vminsh
-
-  vi = vec_nabs(vi);
-// CHECK: sub <4 x i32> zeroinitializer
-// CHECK: @llvm.ppc.altivec.vminsw
-// CHECK-LE: sub <4 x i32> zeroinitializer
-// CHECK-LE: @llvm.ppc.altivec.vminsw
-
-  res_vi = vec_neg(vi);
-// CHECK: sub <4 x i32> zeroinitializer, {{%[0-9]+}}
-// CHECK-LE: sub <4 x i32> zeroinitializer, {{%[0-9]+}}
-// CHECK-NOALTIVEC: error: use of undeclared identifier 'vi'
-// CHECK-NOALTIVEC: vi = vec_neg(vi);
-
-  res_vs = vec_neg(vs);
-// CHECK: sub <8 x i16> zeroinitializer, {{%[0-9]+}}
-// CHECK-LE: sub <8 x i16> zeroinitializer, {{%[0-9]+}}
-// CHECK-NOALTIVEC: error: use of undeclared identifier 'vs'
-// CHECK-NOALTIVEC: res_vs = vec_neg(vs);
-
-  res_vsc = vec_neg(vsc);
-// CHECK: sub <16 x i8> zeroinitializer, {{%[0-9]+}}
-// CHECK-LE: sub <16 x i8> zeroinitializer, {{%[0-9]+}}
-// CHECK-NOALTIVEC: error: use of undeclared identifier 'vsc'
-// CHECK-NOALTIVEC: res_vsc = vec_neg(vsc);
-
-
   /* vec_abs */
   vsc = vec_abss(vsc);
 // CHECK: @llvm.ppc.altivec.vsubsbs
@@ -222,22 +185,6 @@ void test1() {
 // CHECK: fadd <4 x float>
 // CHECK-LE: fadd <4 x float>
 
-  res_vi  = vec_adde(vi, vi, vi);
-// CHECK: and <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK-LE: and <4 x i32>
-// CHECK-LE: add <4 x i32>
-// CHECK-LE: add <4 x i32>
-
-  res_vui  = vec_adde(vui, vui, vui);
-// CHECK: and <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK-LE: and <4 x i32>
-// CHECK-LE: add <4 x i32>
-// CHECK-LE: add <4 x i32>
-
   res_vsc = vec_vaddubm(vsc, vsc);
 // CHECK: add <16 x i8>
 // CHECK-LE: add <16 x i8>
@@ -5326,8 +5273,6 @@ void test6() {
 // CHECK: fsub <4 x float>
 // CHECK-LE: fsub <4 x float>
 
-  
-
   res_vsc = vec_vsububm(vsc, vsc);
 // CHECK: sub <16 x i8>
 // CHECK-LE: sub <16 x i8>
@@ -5409,10 +5354,6 @@ void test6() {
 // CHECK: @llvm.ppc.altivec.vsubcuw
 // CHECK-LE: @llvm.ppc.altivec.vsubcuw
 
-  res_vi = vec_subc(vi, vi);
-// CHECK: @llvm.ppc.altivec.vsubcuw
-// CHECK-LE: @llvm.ppc.altivec.vsubcuw
-
   res_vui = vec_vsubcuw(vui, vui);
 // CHECK: @llvm.ppc.altivec.vsubcuw
 // CHECK-LE: @llvm.ppc.altivec.vsubcuw
@@ -5490,26 +5431,6 @@ void test6() {
 // CHECK: @llvm.ppc.altivec.vsubuws
 // CHECK-LE: @llvm.ppc.altivec.vsubuws
 
-  res_vi = vec_sube(vi, vi, vi);
-// CHECK: and <4 x i32>
-// CHECK: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK: add <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK-LE: and <4 x i32>
-// CHECK-LE: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK-LE: add <4 x i32>
-// CHECK-LE: add <4 x i32>
-
-  res_vui = vec_sube(vui, vui, vui);
-// CHECK: and <4 x i32>
-// CHECK: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK: add <4 x i32>
-// CHECK: add <4 x i32>
-// CHECK-LE: and <4 x i32>
-// CHECK-LE: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK-LE: add <4 x i32>
-// CHECK-LE: add <4 x i32>
-
   res_vsc = vec_vsubsbs(vsc, vsc);
 // CHECK: @llvm.ppc.altivec.vsubsbs
 // CHECK-LE: @llvm.ppc.altivec.vsubsbs
diff --git a/clang/test/CodeGen/builtins-ppc-p8vector.c b/clang/test/CodeGen/builtins-ppc-p8vector.c
index d78c3a7d934..5e16825ac7d 100644
--- a/clang/test/CodeGen/builtins-ppc-p8vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -73,6 +73,13 @@ void test1() {
 // CHECK-LE: call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %{{[0-9]*}}, <2 x i64>
 // CHECK-PPC: error: call to 'vec_abs' is ambiguous
 
+  res_vd = vec_abs(vda);
+// CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}})
+// CHECK: store <2 x double> %{{.*}}, <2 x double>* @res_vd
+// CHECK-LE: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}})
+// CHECK-LE: store <2 x double> %{{.*}}, <2 x double>* @res_vd
+// CHECK-PPC: error: call to 'vec_abs' is ambiguous
+
   /* vec_add */
   res_vsll = vec_add(vsll, vsll);
 // CHECK: add <2 x i64>
@@ -1549,83 +1556,4 @@ void test1() {
 // CHECK: llvm.ppc.altivec.vbpermq
 // CHECK-LE: llvm.ppc.altivec.vbpermq
 // CHECK-PPC: warning: implicit declaration of function 'vec_bperm'
-
-  res_vsll = vec_neg(vsll);
-// CHECK: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
-// CHECK-LE: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
-// CHECK_PPC: call to 'vec_neg' is ambiguous
-
-
-}
-
-
-vector signed int test_vec_addec_signed (vector signed int a, vector signed int b, vector signed int c) {
-  return vec_addec(a, b, c);
-// CHECK-LABEL: @test_vec_addec_signed
-// CHECK-LABEL: for.cond.i:
-// CHECK: icmp slt i32 {{%[0-9]+}}, 4
-// CHECK-LABEL: for.body.i:
-// CHECK: extractelement
-// CHECK: extractelement
-// CHECK: extractelement
-// CHECK: and i32 {{%[0-9]+}}, 1
-// CHECK: zext
-// CHECK: zext
-// CHECK: zext
-// CHECK: add i64
-// CHECK: add i64
-// CHECK: lshr i64
-// CHECK: and i64
-// CHECK: trunc i64 {{%[0-9]+}} to i32
-// CHECK: zext i32
-// CHECK: trunc i64 {{%[0-9]+}} to i32
-// CHECK: sext i32
-// CHECK: add nsw i32
-// CHECK: br label
-// CHECK: ret <4 x i32>
-
-}
-
-
-vector unsigned int test_vec_addec_unsigned (vector unsigned int a, vector unsigned int b, vector unsigned int c) {
-  return vec_addec(a, b, c);
-
-// CHECK-LABEL: @test_vec_addec_unsigned
-// CHECK-LABEL: for.cond.i:
-// CHECK: icmp slt i32 {{%[0-9]+}}, 4
-// CHECK-LABEL: for.body.i:
-// CHECK: extractelement
-// CHECK: and i32
-// CHECK: extractelement
-// CHECK: zext i32
-// CHECK: extractelement
-// CHECK: zext i32
-// CHECK: zext i32
-// CHECK: add i64
-// CHECK: lshr i64
-// CHECK: and i64
-// CHECK: trunc i64 {{%[0-9]+}} to i32
-// CHECK: zext i32
-// CHECK: trunc i64 {{%[0-9]+}} to i32
-// CHECK: sext i32
-// CHECK: add nsw i32
-// CHECK: br label
-// CHECK: ret <4 x i32>
-}
-
-vector signed int test_vec_subec_signed (vector signed int a, vector signed int b, vector signed int c) {
-  return vec_subec(a, b, c);
-// CHECK-LABEL: @test_vec_subec_signed
-// CHECK: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK-LABEL: for.cond.i.i:
-// CHECK: ret <4 x i32>
-}
-
-vector unsigned int test_vec_subec_unsigned (vector unsigned int a, vector unsigned int b, vector unsigned int c) {
-  return vec_subec(a, b, c);
-
-// CHECK-LABEL: @test_vec_subec_unsigned
-// CHECK: xor <4 x i32> {{%[0-9]+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
-// CHECK-LABEL: for.cond.i.i:
-// CHECK: ret <4 x i32>
 }
diff --git a/clang/test/CodeGen/builtins-ppc-quadword.c b/clang/test/CodeGen/builtins-ppc-quadword.c
index 3e168c8b1be..cae1737b6e4 100644
--- a/clang/test/CodeGen/builtins-ppc-quadword.c
+++ b/clang/test/CodeGen/builtins-ppc-quadword.c
@@ -125,32 +125,11 @@ void test1() {
 // CHECK-LE: @llvm.ppc.altivec.vsubeuqm
 // CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int'
   
-  /* vec_sube */
-  res_vlll = vec_sube(vlll, vlll, vlll);
-// CHECK: @llvm.ppc.altivec.vsubeuqm
-// CHECK-LE: @llvm.ppc.altivec.vsubeuqm
-// CHECK-PPC: error: call to 'vec_sube' is ambiguous
-  
-  res_vulll = vec_sube(vulll, vulll, vulll);
-// CHECK: @llvm.ppc.altivec.vsubeuqm
-// CHECK-LE: @llvm.ppc.altivec.vsubeuqm
-// CHECK-PPC: error: call to 'vec_sube' is ambiguous
-  
-  res_vlll = vec_sube(vlll, vlll, vlll);
-// CHECK: @llvm.ppc.altivec.vsubeuqm
-// CHECK-LE: @llvm.ppc.altivec.vsubeuqm
-// CHECK-PPC: error: call to 'vec_sube' is ambiguous
-  
   res_vulll = vec_vsubeuqm(vulll, vulll, vulll);
 // CHECK: @llvm.ppc.altivec.vsubeuqm
 // CHECK-LE: @llvm.ppc.altivec.vsubeuqm
 // CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int'
   
-  res_vulll = vec_sube(vulll, vulll, vulll);
-// CHECK: @llvm.ppc.altivec.vsubeuqm
-// CHECK-LE: @llvm.ppc.altivec.vsubeuqm
-// CHECK-PPC: error: call to 'vec_sube' is ambiguous
-
   /* vec_subc */
   res_vlll = vec_subc(vlll, vlll);
 // CHECK: @llvm.ppc.altivec.vsubcuq
@@ -177,19 +156,9 @@ void test1() {
   res_vlll = vec_vsubecuq(vlll, vlll, vlll);
 // CHECK: @llvm.ppc.altivec.vsubecuq
 // CHECK-LE: @llvm.ppc.altivec.vsubecuq
-// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int'
-
-  res_vulll = vec_vsubecuq(vulll, vulll, vulll);
-// CHECK: @llvm.ppc.altivec.vsubecuq
-// CHECK-LE: @llvm.ppc.altivec.vsubecuq
-// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int'
-
-  res_vlll = vec_subec(vlll, vlll, vlll);
-// CHECK: @llvm.ppc.altivec.vsubecuq
-// CHECK-LE: @llvm.ppc.altivec.vsubecuq
 // CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int'  
 
-  res_vulll = vec_subec(vulll, vulll, vulll);
+  res_vulll = vec_vsubecuq(vulll, vulll, vulll);
 // CHECK: @llvm.ppc.altivec.vsubecuq
 // CHECK-LE: @llvm.ppc.altivec.vsubecuq
 // CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int'  
diff --git a/clang/test/CodeGen/builtins-ppc-vsx.c b/clang/test/CodeGen/builtins-ppc-vsx.c
index 16c72c404d9..5a95eb9798a 100644
--- a/clang/test/CodeGen/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/builtins-ppc-vsx.c
@@ -70,18 +70,6 @@ void test1() {
 // CHECK: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
 // CHECK-LE: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
 
-  res_vd = vec_abs(vd);
-// CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
-// CHECK-LE: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
-
-  res_vf = vec_nabs(vf);
-// CHECK: [[VEC:%[0-9]+]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
-// CHECK-NEXT: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[VEC]]
-
-  res_vd = vec_nabs(vd);
-// CHECK: [[VECD:%[0-9]+]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
-// CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, [[VECD]]
-
   dummy();
 // CHECK: call void @dummy()
 // CHECK-LE: call void @dummy()
@@ -1683,12 +1671,4 @@ vec_xst_be(vull, sll, aull);
 vec_xst_be(vd, sll, ad);
 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
-
-  res_vf = vec_neg(vf);
-// CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, {{%[0-9]+}}
-// CHECK-LE: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, {{%[0-9]+}}
-
-  res_vd = vec_neg(vd);
-// CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, {{%[0-9]+}}
-// CHECK-LE: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, {{%[0-9]+}}
 }