summaryrefslogtreecommitdiffstats
path: root/clang/test
diff options
context:
space:
mode:
authorYi Kong <Yi.Kong@arm.com>2014-07-03 16:01:25 +0000
committerYi Kong <Yi.Kong@arm.com>2014-07-03 16:01:25 +0000
commit4efadfb0b0ec545d0ef609c5eeb6a0342d0e56e4 (patch)
treee0d654ac689692faca5d56aeccf3fba730da6ad7 /clang/test
parent93e52da641d66ca01c26c236cfab641ca405dd9d (diff)
downloadbcm5719-llvm-4efadfb0b0ec545d0ef609c5eeb6a0342d0e56e4.tar.gz
bcm5719-llvm-4efadfb0b0ec545d0ef609c5eeb6a0342d0e56e4.zip
[ARM] Implement ISB memory barrier intrinsic
Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212277
Diffstat (limited to 'clang/test')
-rw-r--r--clang/test/CodeGen/builtins-arm.c1
-rw-r--r--clang/test/Sema/builtins-arm.c6
2 files changed, 7 insertions, 0 deletions
diff --git a/clang/test/CodeGen/builtins-arm.c b/clang/test/CodeGen/builtins-arm.c
index 7b7207299e3..e55183c7f6a 100644
--- a/clang/test/CodeGen/builtins-arm.c
+++ b/clang/test/CodeGen/builtins-arm.c
@@ -52,6 +52,7 @@ void sevl() {
void test_barrier() {
__builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.arm.dmb(i32 1)
__builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.arm.dsb(i32 2)
+ __builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.arm.isb(i32 3)
}
// CHECK: call {{.*}} @llvm.arm.rbit(i32 %a)
diff --git a/clang/test/Sema/builtins-arm.c b/clang/test/Sema/builtins-arm.c
index 3ac1da0aa93..6c367d35a5f 100644
--- a/clang/test/Sema/builtins-arm.c
+++ b/clang/test/Sema/builtins-arm.c
@@ -31,4 +31,10 @@ void test2() {
*ptr = '0'; // expected-error {{incomplete type 'void' is not assignable}}
}
+void test3() {
+ __builtin_arm_dsb(16); // expected-error {{argument should be a value from 0 to 15}}
+ __builtin_arm_dmb(17); // expected-error {{argument should be a value from 0 to 15}}
+ __builtin_arm_isb(18); // expected-error {{argument should be a value from 0 to 15}}
+}
+
#endif
OpenPOWER on IntegriCloud