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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2017-05-09 16:24:03 +0000 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2017-05-09 16:24:03 +0000 |
| commit | 125c03070edbe7ee8b4f66879a08dc80cd280584 (patch) | |
| tree | e3a5ba9111ce1dc828a0d8dc0f65f5d7bea7911b /clang/test | |
| parent | 0c42d8c35ba6acd4d3620915c64af5a7badc1e73 (diff) | |
| download | bcm5719-llvm-125c03070edbe7ee8b4f66879a08dc80cd280584.tar.gz bcm5719-llvm-125c03070edbe7ee8b4f66879a08dc80cd280584.zip | |
[mips] Impose a threshold for coercion of aggregates
Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate
structures only if the size of said aggregate is less than 16/64 bytes,
depending on the ABI.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D32900
llvm-svn: 302547
Diffstat (limited to 'clang/test')
| -rw-r--r-- | clang/test/CodeGen/mips-aggregate-arg.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/clang/test/CodeGen/mips-aggregate-arg.c b/clang/test/CodeGen/mips-aggregate-arg.c new file mode 100644 index 00000000000..b0be458ec6a --- /dev/null +++ b/clang/test/CodeGen/mips-aggregate-arg.c @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
|
