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authorAlexey Bataev <a.bataev@hotmail.com>2016-04-19 16:27:55 +0000
committerAlexey Bataev <a.bataev@hotmail.com>2016-04-19 16:27:55 +0000
commit823acfacdfef94ebc5f97e913bfbdac535a0d2bc (patch)
treec30976ab309667c22c3e72659fe0e9872815ce2f /clang/test/OpenMP/task_private_codegen.cpp
parentf7d9b263844c731f5872a502f33d03f48d38cf6c (diff)
downloadbcm5719-llvm-823acfacdfef94ebc5f97e913bfbdac535a0d2bc.tar.gz
bcm5719-llvm-823acfacdfef94ebc5f97e913bfbdac535a0d2bc.zip
[OPENMP] Codegen for untied tasks.
If the untied clause is present on a task construct, any thread in the team can resume the task region after a suspension. Patch adds proper codegen for untied tasks. llvm-svn: 266754
Diffstat (limited to 'clang/test/OpenMP/task_private_codegen.cpp')
-rw-r--r--clang/test/OpenMP/task_private_codegen.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/clang/test/OpenMP/task_private_codegen.cpp b/clang/test/OpenMP/task_private_codegen.cpp
index 1455fd11a91..a2dc8423264 100644
--- a/clang/test/OpenMP/task_private_codegen.cpp
+++ b/clang/test/OpenMP/task_private_codegen.cpp
@@ -331,10 +331,11 @@ int main() {
// CHECK: define internal i32 [[TASK_ENTRY]](i32, [[KMP_TASK_TMAIN_TY]]* noalias)
-// CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
-// CHECK: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
-// CHECK: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]]*,
-// CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
+// CHECK: alloca i32*,
+// CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
+// CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
+// CHECK-DAG: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]]*,
+// CHECK-DAG: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
// CHECK: store void (i8*, ...)* bitcast (void ([[PRIVATES_TMAIN_TY]]*, i32**, [2 x i32]**, [2 x [[S_INT_TY]]]**, [[S_INT_TY]]**)* [[PRIVATES_MAP_FN]] to void (i8*, ...)*), void (i8*, ...)** [[MAP_FN_ADDR:%.+]],
// CHECK: [[MAP_FN:%.+]] = load void (i8*, ...)*, void (i8*, ...)** [[MAP_FN_ADDR]],
// CHECK: call void (i8*, ...) [[MAP_FN]](i8* %{{.+}}, i32** [[PRIV_T_VAR_ADDR]], [2 x i32]** [[PRIV_VEC_ADDR]], [2 x [[S_INT_TY]]]** [[PRIV_S_ARR_ADDR]], [[S_INT_TY]]** [[PRIV_VAR_ADDR]])
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