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author | Alexey Bataev <a.bataev@hotmail.com> | 2015-06-16 13:14:42 +0000 |
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committer | Alexey Bataev <a.bataev@hotmail.com> | 2015-06-16 13:14:42 +0000 |
commit | fc087ecc051e52229cc0af176436005d97152ef3 (patch) | |
tree | 798ee933f7a1a092e36fccf12970fd495ba5db67 /clang/test/OpenMP/simd_codegen.cpp | |
parent | 8d8b13dc19d5f031a04ba1393be70e7be37dd561 (diff) | |
download | bcm5719-llvm-fc087ecc051e52229cc0af176436005d97152ef3.tar.gz bcm5719-llvm-fc087ecc051e52229cc0af176436005d97152ef3.zip |
[OPENMP] Support lastprivate clause in omp simd directive.
Added codegen for lastprivate clauses within simd loop-based directives.
llvm-svn: 239813
Diffstat (limited to 'clang/test/OpenMP/simd_codegen.cpp')
-rw-r--r-- | clang/test/OpenMP/simd_codegen.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/clang/test/OpenMP/simd_codegen.cpp b/clang/test/OpenMP/simd_codegen.cpp index 6b3170d5dfd..0a5b38a0ce3 100644 --- a/clang/test/OpenMP/simd_codegen.cpp +++ b/clang/test/OpenMP/simd_codegen.cpp @@ -182,6 +182,8 @@ void simple(float *a, float *b, float *c, float *d) { } int A; + // CHECK: store i32 -1, i32* [[A:%.+]], + A = -1; #pragma omp simd lastprivate(A) // Clause 'lastprivate' implementation is not completed yet. // Test checks that one iteration is separated in presence of lastprivate. @@ -198,13 +200,18 @@ void simple(float *a, float *b, float *c, float *d) { // CHECK: [[IV7_0:%.+]] = load i64, i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] // CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i64 [[IV7_0]], 3 // CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i64 -10, [[LC_IT_1]] -// CHECK-NEXT: store i64 [[LC_IT_2]], i64* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] +// CHECK-NEXT: store i64 [[LC_IT_2]], i64* [[LC:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] +// CHECK-NEXT: [[LC_VAL:%.+]] = load i64, i64* [[LC]]{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] +// CHECK-NEXT: [[CONV:%.+]] = trunc i64 [[LC_VAL]] to i32 +// CHECK-NEXT: store i32 [[CONV]], i32* [[A_PRIV:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] A = i; // CHECK: [[IV7_2:%.+]] = load i64, i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] // CHECK-NEXT: [[ADD7_2:%.+]] = add nsw i64 [[IV7_2]], 1 // CHECK-NEXT: store i64 [[ADD7_2]], i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] } // CHECK: [[SIMPLE_LOOP7_END]] +// CHECK-NEXT: [[A_PRIV_VAL:%.+]] = load i32, i32* [[A_PRIV]], +// CHECK-NEXT: store i32 [[A_PRIV_VAL]], i32* [[A]], // CHECK-NEXT: ret void } |