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authorPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-03-01 07:35:57 +0000
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-03-01 07:35:57 +0000
commit9bf43b5c261b4df6c855231905d14608687c7633 (patch)
treeb21a50b15fb749aaf4be729710c2f598a0d16820 /clang/test/Frontend/print-header-includes.c
parenta48285a1900ed17b019ef291ecae743a91d2f8b6 (diff)
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[MIPS GlobalISel] Fix mul operands
Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355178
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