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| author | Alex Bradbury <asb@lowrisc.org> | 2018-01-15 17:54:52 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-01-15 17:54:52 +0000 |
| commit | 8cbdd4892fcd030965bd10f36d3484cb82bee329 (patch) | |
| tree | 47fbde790a31d54a3debaf103ea55e21c14b3bb4 /clang/test/Driver/riscv32-toolchain.c | |
| parent | 674f9128b7520ad43d3358724baf0f89baeeda02 (diff) | |
| download | bcm5719-llvm-8cbdd4892fcd030965bd10f36d3484cb82bee329.tar.gz bcm5719-llvm-8cbdd4892fcd030965bd10f36d3484cb82bee329.zip | |
[RISCV] Implement RISCV ABI lowering
RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64.
Unfortunately we need to count argument registers in the frontend in order to
determine when to emit signext and zeroext attributes. Integer scalars are
extended according to their type up to 32-bits and then sign-extended to XLen
when passed in registers, but are anyext when passed on the stack. This patch
only implements the base integer (soft float) ABIs.
For more information on the RISC-V ABI, see [the ABI
doc](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md),
my [golden model](https://github.com/lowRISC/riscv-calling-conv-model), and
the [LLVM RISC-V calling convention
patch](https://reviews.llvm.org/D39898#2d1595b4) (specifically the comment
documenting frontend expectations).
Differential Revision: https://reviews.llvm.org/D40023
llvm-svn: 322494
Diffstat (limited to 'clang/test/Driver/riscv32-toolchain.c')
| -rw-r--r-- | clang/test/Driver/riscv32-toolchain.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/clang/test/Driver/riscv32-toolchain.c b/clang/test/Driver/riscv32-toolchain.c index efe550e0f29..3839f8e59c9 100644 --- a/clang/test/Driver/riscv32-toolchain.c +++ b/clang/test/Driver/riscv32-toolchain.c @@ -73,3 +73,50 @@ int align_ld = __alignof(long double); // CHECK: @align_vl = global i32 4 int align_vl = __alignof(va_list); + +// Check types + +// CHECK: zeroext i8 @check_char() +char check_char() { return 0; } + +// CHECK: define signext i16 @check_short() +short check_short() { return 0; } + +// CHECK: define i32 @check_int() +int check_int() { return 0; } + +// CHECK: define i32 @check_wchar_t() +int check_wchar_t() { return 0; } + +// CHECK: define i32 @check_long() +long check_long() { return 0; } + +// CHECK: define i64 @check_longlong() +long long check_longlong() { return 0; } + +// CHECK: define zeroext i8 @check_uchar() +unsigned char check_uchar() { return 0; } + +// CHECK: define zeroext i16 @check_ushort() +unsigned short check_ushort() { return 0; } + +// CHECK: define i32 @check_uint() +unsigned int check_uint() { return 0; } + +// CHECK: define i32 @check_ulong() +unsigned long check_ulong() { return 0; } + +// CHECK: define i64 @check_ulonglong() +unsigned long long check_ulonglong() { return 0; } + +// CHECK: define i32 @check_size_t() +size_t check_size_t() { return 0; } + +// CHECK: define float @check_float() +float check_float() { return 0; } + +// CHECK: define double @check_double() +double check_double() { return 0; } + +// CHECK: define fp128 @check_longdouble() +long double check_longdouble() { return 0; } |

