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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-01-05 17:02:28 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-01-05 17:02:28 +0000 |
| commit | f964df3640cc43aa3e7c3555dcfb349b39757fa7 (patch) | |
| tree | 4fc6b3dea147e1d58a2c2bbc1980f8ab38f95a5e /clang/test/Driver/gcc-version-debug.c | |
| parent | 45ed4f954265175849efdd0d45940a64395b44d0 (diff) | |
| download | bcm5719-llvm-f964df3640cc43aa3e7c3555dcfb349b39757fa7.tar.gz bcm5719-llvm-f964df3640cc43aa3e7c3555dcfb349b39757fa7.zip | |
[AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.
For 0-lane stores, we used to generate code similar to:
fmov w8, s0
str w8, [x0, x1, lsl #2]
instead of:
str s0, [x0, x1, lsl #2]
To correct that: for store lane 0 patterns, directly match to STR <subreg>0.
Byte-sized instructions don't have the special case for a 0 index,
because FPR8s are defined to have untyped content.
rdar://16372710
Differential Revision: http://reviews.llvm.org/D6772
llvm-svn: 225181
Diffstat (limited to 'clang/test/Driver/gcc-version-debug.c')
0 files changed, 0 insertions, 0 deletions
