diff options
| author | Michael Kruse <llvm@meinersbur.de> | 2018-12-20 21:24:54 +0000 |
|---|---|---|
| committer | Michael Kruse <llvm@meinersbur.de> | 2018-12-20 21:24:54 +0000 |
| commit | 0535137e4ad5fc76b19ec6118724f66023f565f7 (patch) | |
| tree | 450b4a084973a76d4b7237bc355664aa19dd9255 /clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp | |
| parent | a6b9c68a85df16560c4a20a918321d0a847971cd (diff) | |
| download | bcm5719-llvm-0535137e4ad5fc76b19ec6118724f66023f565f7.tar.gz bcm5719-llvm-0535137e4ad5fc76b19ec6118724f66023f565f7.zip | |
[CodeGen] Generate llvm.loop.parallel_accesses instead of llvm.mem.parallel_loop_access metadata.
Instead of generating llvm.mem.parallel_loop_access metadata, generate
llvm.access.group on instructions and llvm.loop.parallel_accesses on
loops. There is one access group per generated loop.
This is clang part of D52116/r349725.
Differential Revision: https://reviews.llvm.org/D52117
llvm-svn: 349823
Diffstat (limited to 'clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp')
| -rw-r--r-- | clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp b/clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp new file mode 100644 index 00000000000..da060f7902e --- /dev/null +++ b/clang/test/CodeGenCXX/pragma-loop-safety-imperfectly_nested.cpp @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -triple x86_64-apple-darwin -std=c++11 -emit-llvm -o - %s | FileCheck %s + +// Verify that the outer loop has the llvm.access.group property for the +// accesses outside and inside the inner loop, even when the inner loop +// is not perfectly nested. +void vectorize_imperfectly_nested_test(int *List, int Length) { +#pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable) + for (int i = 0; i < Length; ++i) { + List[i * Length] = 42; +#pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable) + for (int j = 1; j < Length - 1; ++j) + List[i * Length + j] = (i + j) * 2; + List[(i + 1) * Length - 1] = 21; + } +} + + +// CHECK: load i32, i32* %Length.addr, align 4, !llvm.access.group ![[ACCESS_GROUP_2:[0-9]+]] + +// CHECK: %[[MUL:.+]] = mul nsw i32 %add, 2 +// CHECK: store i32 %[[MUL]], i32* %{{.+}}, !llvm.access.group ![[ACCESS_GROUP_3:[0-9]+]] +// CHECK: br label %{{.+}}, !llvm.loop ![[INNER_LOOPID:[0-9]+]] +// CHECK: store i32 21, i32* %{{.+}}, !llvm.access.group ![[ACCESS_GROUP_2]] +// CHECK: br label %{{.+}}, !llvm.loop ![[OUTER_LOOPID:[0-9]+]] + +// CHECK: ![[ACCESS_GROUP_2]] = distinct !{} +// CHECK: ![[ACCESS_GROUP_LIST_3:[0-9]+]] = !{![[ACCESS_GROUP_2]], ![[ACCESS_GROUP_4:[0-9]+]]} +// CHECK: ![[ACCESS_GROUP_4]] = distinct !{} +// CHECK: ![[INNER_LOOPID]] = distinct !{![[INNER_LOOPID]], {{.*}} ![[PARALLEL_ACCESSES_8:[0-9]+]]} +// CHECK: ![[PARALLEL_ACCESSES_8]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_4]]} +// CHECK: ![[OUTER_LOOPID]] = distinct !{![[OUTER_LOOPID]], {{.*}} ![[PARALLEL_ACCESSES_10:[0-9]+]]} +// CHECK: ![[PARALLEL_ACCESSES_10]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_2]]} |
