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authorAndrew Kaylor <andrew.kaylor@intel.com>2017-02-13 23:38:52 +0000
committerAndrew Kaylor <andrew.kaylor@intel.com>2017-02-13 23:38:52 +0000
commit709f1c2a9bf8482ba457a7e16fee0400bc889a1e (patch)
tree67470d6e7782daa47dde99ae81f579429824004b /clang/test/CodeGenCXX/new-array-init.cpp
parent46eed9d625e65fc55baf3030c5edc1a0407de215 (diff)
downloadbcm5719-llvm-709f1c2a9bf8482ba457a7e16fee0400bc889a1e.tar.gz
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[X86] Add MXCSR register
This adds MXCSR to the set of recognized registers for X86 targets and updates the instructions that read or write it. I do not intend for all of the various floating point instructions that implicitly use the control bits or update the status bits of this register to ever have that usage modeled by default. However, when constrained floating point modes (such as strict FP exception status modeling or dynamic rounding modes) are enabled, implicit use/def information for MXCSR will be added to those instructions. Until those additional updates are made this should cause (almost?) no functional changes. Theoretically, this will prevent instructions like LDMXCSR and STMXCSR from being moved past one another, but that should be prevented anyway and I haven't found a case where it is happening now. Differential Revision: https://reviews.llvm.org/D29903 llvm-svn: 295004
Diffstat (limited to 'clang/test/CodeGenCXX/new-array-init.cpp')
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