Emit DeferredDeclsToEmit in a DFS order.

Currently we emit DeferredDeclsToEmit in reverse order. This patch changes that.

The advantages of the change are that

* The output order is a bit closer to the source order. The change to
test/CodeGenCXX/pod-member-memcpys.cpp is a good example.

* If we decide to deffer more, it will not cause as large changes in the
estcases as it would without this patch.

llvm-svn: 226751

1 files changed, 9 insertions, 9 deletions

diff --git a/clang/test/CodeGenCXX/lambda-expressions.cpp b/clang/test/CodeGenCXX/lambda-expressions.cpp
index 9afd20da1b1..7fb22988faa 100644
--- a/clang/test/CodeGenCXX/lambda-expressions.cpp
+++ b/clang/test/CodeGenCXX/lambda-expressions.cpp
@@ -99,14 +99,7 @@ int *PR22071_fun() {
   return [&] { return &y; }();
 }
 
-// CHECK-LABEL: define internal void @"_ZZ1hvEN3$_98__invokeEv"(%struct.A* noalias sret %agg.result) {{.*}} {
-// CHECK-NOT: =
-// CHECK: call void @"_ZZ1hvENK3$_9clEv"(%struct.A* sret %agg.result,
-// CHECK-NEXT: ret void
-struct A { ~A(); };
-void h() {
-  A (*h)() = [] { return A(); };
-}
+// CHECK-LABEL: define internal void @"_ZZ1e1ES_bEN3$_4D2Ev"
 
 // CHECK-LABEL: define internal i32 @"_ZZ1fvEN3$_58__invokeEii"
 // CHECK: store i32
@@ -116,7 +109,14 @@ void h() {
 // CHECK-NEXT: call i32 @"_ZZ1fvENK3$_5clEii"
 // CHECK-NEXT: ret i32
 
-// CHECK-LABEL: define internal void @"_ZZ1e1ES_bEN3$_4D2Ev"
+// CHECK-LABEL: define internal void @"_ZZ1hvEN3$_98__invokeEv"(%struct.A* noalias sret %agg.result) {{.*}} {
+// CHECK-NOT: =
+// CHECK: call void @"_ZZ1hvENK3$_9clEv"(%struct.A* sret %agg.result,
+// CHECK-NEXT: ret void
+struct A { ~A(); };
+void h() {
+  A (*h)() = [] { return A(); };
+}
 
 // <rdar://problem/12778708>
 struct XXX {};