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authorGuanzhong Chen <gzchen@google.com>2019-08-15 19:33:36 +0000
committerGuanzhong Chen <gzchen@google.com>2019-08-15 19:33:36 +0000
commit82bfd1d25712f8c1b714614f3df559c773f08988 (patch)
tree59a24f8d01e797433cbc2225343ef792cc9ba3a5 /clang/test/CodeGen/wasm-varargs.c
parent0c476111317cb7aaa9a3e9f75e1c35f83122ee26 (diff)
downloadbcm5719-llvm-82bfd1d25712f8c1b714614f3df559c773f08988.tar.gz
bcm5719-llvm-82bfd1d25712f8c1b714614f3df559c773f08988.zip
[WebAssembly] Correctly handle va_arg of zero-sized structures
Summary: D66168 passes size 0 structs indirectly, while the wasm backend expects it to be passed directly. This causes subsequent variadic arguments to be read incorrectly. This diff changes it so that size 0 structs are passed directly. Reviewers: dschuff, tlively, sbc100 Reviewed By: dschuff Subscribers: jgravelle-google, aheejin, sunfish, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66255 llvm-svn: 369042
Diffstat (limited to 'clang/test/CodeGen/wasm-varargs.c')
-rw-r--r--clang/test/CodeGen/wasm-varargs.c76
1 files changed, 58 insertions, 18 deletions
diff --git a/clang/test/CodeGen/wasm-varargs.c b/clang/test/CodeGen/wasm-varargs.c
index fa672064d0f..23506875ac9 100644
--- a/clang/test/CodeGen/wasm-varargs.c
+++ b/clang/test/CodeGen/wasm-varargs.c
@@ -80,21 +80,61 @@ struct S test_struct(char *fmt, ...) {
return v;
}
-// CHECK: define void @test_struct([[STRUCT_S:%[^,=]+]]*{{.*}} noalias sret [[AGG_RESULT:%.*]], i8*{{.*}} %fmt, ...) {{.*}} {
-// CHECK: [[FMT_ADDR:%[^,=]+]] = alloca i8*, align 4
-// CHECK: [[VA:%[^,=]+]] = alloca i8*, align 4
-// CHECK: store i8* %fmt, i8** [[FMT_ADDR]], align 4
-// CHECK: [[VA1:%[^,=]+]] = bitcast i8** [[VA]] to i8*
-// CHECK: call void @llvm.va_start(i8* [[VA1]])
-// CHECK: [[ARGP_CUR:%[^,=]+]] = load i8*, i8** [[VA]], align 4
-// CHECK: [[ARGP_NEXT:%[^,=]+]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4
-// CHECK: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
-// CHECK: [[R3:%[^,=]+]] = bitcast i8* [[ARGP_CUR]] to [[STRUCT_S]]**
-// CHECK: [[R4:%[^,=]+]] = load [[STRUCT_S]]*, [[STRUCT_S]]** %0, align 4
-// CHECK: [[R5:%[^,=]+]] = bitcast [[STRUCT_S]]* [[AGG_RESULT]] to i8*
-// CHECK: [[R6:%[^,=]+]] = bitcast [[STRUCT_S]]* [[R4]] to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[R5]], i8* align 4 [[R6]], i32 12, i1 false)
-// CHECK: [[VA2:%[^,=]+]] = bitcast i8** [[VA]] to i8*
-// CHECK: call void @llvm.va_end(i8* [[VA2]])
-// CHECK: ret void
-// CHECK: }
+// CHECK: define void @test_struct([[STRUCT_S:%[^,=]+]]*{{.*}} noalias sret [[AGG_RESULT:%.*]], i8*{{.*}} %fmt, ...) {{.*}} {
+// CHECK: [[FMT_ADDR:%[^,=]+]] = alloca i8*, align 4
+// CHECK-NEXT: [[VA:%[^,=]+]] = alloca i8*, align 4
+// CHECK-NEXT: store i8* %fmt, i8** [[FMT_ADDR]], align 4
+// CHECK-NEXT: [[VA1:%[^,=]+]] = bitcast i8** [[VA]] to i8*
+// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]])
+// CHECK-NEXT: [[ARGP_CUR:%[^,=]+]] = load i8*, i8** [[VA]], align 4
+// CHECK-NEXT: [[ARGP_NEXT:%[^,=]+]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4
+// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
+// CHECK-NEXT: [[R3:%[^,=]+]] = bitcast i8* [[ARGP_CUR]] to [[STRUCT_S]]**
+// CHECK-NEXT: [[R4:%[^,=]+]] = load [[STRUCT_S]]*, [[STRUCT_S]]** [[R3]], align 4
+// CHECK-NEXT: [[R5:%[^,=]+]] = bitcast [[STRUCT_S]]* [[AGG_RESULT]] to i8*
+// CHECK-NEXT: [[R6:%[^,=]+]] = bitcast [[STRUCT_S]]* [[R4]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[R5]], i8* align 4 [[R6]], i32 12, i1 false)
+// CHECK-NEXT: [[VA2:%[^,=]+]] = bitcast i8** [[VA]] to i8*
+// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]])
+// CHECK-NEXT: ret void
+// CHECK-NEXT: }
+
+struct Z {};
+
+struct S test_empty_struct(char *fmt, ...) {
+ va_list va;
+
+ va_start(va, fmt);
+ struct Z u = va_arg(va, struct Z);
+ struct S v = va_arg(va, struct S);
+ va_end(va);
+
+ return v;
+}
+
+// CHECK: define void @test_empty_struct([[STRUCT_S:%[^,=]+]]*{{.*}} noalias sret [[AGG_RESULT:%.*]], i8*{{.*}} %fmt, ...) {{.*}} {
+// CHECK: [[FMT_ADDR:%[^,=]+]] = alloca i8*, align 4
+// CHECK-NEXT: [[VA:%[^,=]+]] = alloca i8*, align 4
+// CHECK-NEXT: [[U:%[^,=]+]] = alloca [[STRUCT_Z:%[^,=]+]], align 1
+// CHECK-NEXT: store i8* %fmt, i8** [[FMT_ADDR]], align 4
+// CHECK-NEXT: [[VA1:%[^,=]+]] = bitcast i8** [[VA]] to i8*
+// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]])
+// CHECK-NEXT: [[ARGP_CUR:%[^,=]+]] = load i8*, i8** [[VA]], align 4
+// CHECK-NEXT: [[ARGP_NEXT:%[^,=]+]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 0
+// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
+// CHECK-NEXT: [[R0:%[^,=]+]] = bitcast i8* [[ARGP_CUR]] to [[STRUCT_Z]]*
+// CHECK-NEXT: [[R1:%[^,=]+]] = bitcast [[STRUCT_Z]]* [[U]] to i8*
+// CHECK-NEXT: [[R2:%[^,=]+]] = bitcast [[STRUCT_Z]]* [[R0]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 [[R1]], i8* align 4 [[R2]], i32 0, i1 false)
+// CHECK-NEXT: [[ARGP_CUR2:%[^,=]+]] = load i8*, i8** [[VA]], align 4
+// CHECK-NEXT: [[ARGP_NEXT2:%[^,=]+]] = getelementptr inbounds i8, i8* [[ARGP_CUR2]], i32 4
+// CHECK-NEXT: store i8* [[ARGP_NEXT2]], i8** [[VA]], align 4
+// CHECK-NEXT: [[R3:%[^,=]+]] = bitcast i8* [[ARGP_CUR2]] to [[STRUCT_S]]**
+// CHECK-NEXT: [[R4:%[^,=]+]] = load [[STRUCT_S]]*, [[STRUCT_S]]** [[R3]], align 4
+// CHECK-NEXT: [[R5:%[^,=]+]] = bitcast [[STRUCT_S]]* [[AGG_RESULT]] to i8*
+// CHECK-NEXT: [[R6:%[^,=]+]] = bitcast [[STRUCT_S]]* [[R4]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[R5]], i8* align 4 [[R6]], i32 12, i1 false)
+// CHECK-NEXT: [[VA2:%[^,=]+]] = bitcast i8** [[VA]] to i8*
+// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]])
+// CHECK-NEXT: ret void
+// CHECK-NEXT: }
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