[clang][ARM] Fix msvc arm{64} builtins to use int on LP64 systems.

The `InterlockedX_{acq,nf,rel}` functions deal with 32 bits which is long on
MSVC, but int on most other systems.

This also checks that `ReadStatusRegister` and `WriteStatusRegister` have
the correct type on aarch64-darwin.

Differential Revision: https://reviews.llvm.org/D64164

llvm-svn: 367479

1 files changed, 220 insertions, 0 deletions

diff --git a/clang/test/CodeGen/ms-intrinsics-other.c b/clang/test/CodeGen/ms-intrinsics-other.c
index adc8ac98e57..33f81158730 100644
--- a/clang/test/CodeGen/ms-intrinsics-other.c
+++ b/clang/test/CodeGen/ms-intrinsics-other.c
@@ -4,6 +4,15 @@
 // RUN: %clang_cc1 -ffreestanding -fms-extensions \
 // RUN:         -triple x86_64--linux -Oz -emit-llvm %s -o - \
 // RUN:         | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding -fms-extensions \
+// RUN:         -triple aarch64--darwin -Oz -emit-llvm %s -o - \
+// RUN:         | FileCheck %s --check-prefix=CHECK-ARM-ARM64
+// RUN: %clang_cc1 -ffreestanding -fms-extensions \
+// RUN:         -triple aarch64--darwin -Oz -emit-llvm %s -o - \
+// RUN:         | FileCheck %s --check-prefix=CHECK-ARM
+// RUN: %clang_cc1 -ffreestanding -fms-extensions \
+// RUN:         -triple armv7--darwin -Oz -emit-llvm %s -o - \
+// RUN:         | FileCheck %s --check-prefix=CHECK-ARM
 
 // LP64 targets use 'long' as 'int' for MS intrinsics (-fms-extensions)
 #ifdef __LP64__
@@ -196,3 +205,214 @@ unsigned __int64 test__popcnt64(unsigned __int64 x) {
 // CHECK:  [[RESULT:%[0-9]+]] = tail call i64 @llvm.ctpop.i64(i64 %x)
 // CHECK: ret i64 [[RESULT]]
 // CHECK: }
+
+#if defined(__aarch64__)
+LONG test_InterlockedAdd(LONG volatile *Addend, LONG Value) {
+  return _InterlockedAdd(Addend, Value);
+}
+
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(i32*{{[a-z_ ]*}}%Addend, i32 %Value) {{.*}} {
+// CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add i32* %Addend, i32 %Value seq_cst
+// CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value
+// CHECK-ARM-ARM64: ret i32 %[[NEWVAL:[0-9]+]]
+#endif
+
+#if defined(__arm__) || defined(__aarch64__)
+LONG test_InterlockedExchangeAdd_acq(LONG volatile *value, LONG mask) {
+  return _InterlockedExchangeAdd_acq(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask acquire
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+LONG test_InterlockedExchangeAdd_rel(LONG volatile *value, LONG mask) {
+  return _InterlockedExchangeAdd_rel(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask release
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+LONG test_InterlockedExchangeAdd_nf(LONG volatile *value, LONG mask) {
+  return _InterlockedExchangeAdd_nf(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchangeAdd_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask monotonic
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedExchange_acq(LONG volatile *value, LONG mask) {
+  return _InterlockedExchange_acq(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask acquire
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+LONG test_InterlockedExchange_rel(LONG volatile *value, LONG mask) {
+  return _InterlockedExchange_rel(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask release
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+LONG test_InterlockedExchange_nf(LONG volatile *value, LONG mask) {
+  return _InterlockedExchange_nf(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedExchange_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask monotonic
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedCompareExchange_acq(LONG volatile *Destination, LONG Exchange, LONG Comperand) {
+  return _InterlockedCompareExchange_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_acq(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange acquire acquire
+// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedCompareExchange_rel(LONG volatile *Destination, LONG Exchange, LONG Comperand) {
+  return _InterlockedCompareExchange_rel(Destination, Exchange, Comperand);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_rel(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange release monotonic
+// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedCompareExchange_nf(LONG volatile *Destination, LONG Exchange, LONG Comperand) {
+  return _InterlockedCompareExchange_nf(Destination, Exchange, Comperand);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedCompareExchange_nf(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange monotonic monotonic
+// CHECK-ARM: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedOr_acq(LONG volatile *value, LONG mask) {
+  return _InterlockedOr_acq(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask acquire
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedOr_rel(LONG volatile *value, LONG mask) {
+  return _InterlockedOr_rel(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask release
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedOr_nf(LONG volatile *value, LONG mask) {
+  return _InterlockedOr_nf(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedOr_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask monotonic
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedXor_acq(LONG volatile *value, LONG mask) {
+  return _InterlockedXor_acq(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask acquire
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedXor_rel(LONG volatile *value, LONG mask) {
+  return _InterlockedXor_rel(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask release
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedXor_nf(LONG volatile *value, LONG mask) {
+  return _InterlockedXor_nf(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedXor_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask monotonic
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedAnd_acq(LONG volatile *value, LONG mask) {
+  return _InterlockedAnd_acq(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask acquire
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedAnd_rel(LONG volatile *value, LONG mask) {
+  return _InterlockedAnd_rel(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask release
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+LONG test_InterlockedAnd_nf(LONG volatile *value, LONG mask) {
+  return _InterlockedAnd_nf(value, mask);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedAnd_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask monotonic
+// CHECK-ARM:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM: }
+
+
+LONG test_InterlockedIncrement_acq(LONG volatile *Addend) {
+  return _InterlockedIncrement_acq(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 acquire
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedIncrement_rel(LONG volatile *Addend) {
+  return _InterlockedIncrement_rel(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 release
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedIncrement_nf(LONG volatile *Addend) {
+  return _InterlockedIncrement_nf(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedIncrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 monotonic
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedDecrement_acq(LONG volatile *Addend) {
+  return _InterlockedDecrement_acq(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 acquire
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedDecrement_rel(LONG volatile *Addend) {
+  return _InterlockedDecrement_rel(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 release
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+
+LONG test_InterlockedDecrement_nf(LONG volatile *Addend) {
+  return _InterlockedDecrement_nf(Addend);
+}
+// CHECK-ARM: define{{.*}}i32 @test_InterlockedDecrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 monotonic
+// CHECK-ARM: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM: ret i32 [[RESULT]]
+// CHECK-ARM: }
+#endif