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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-10-24 14:42:42 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-10-24 14:42:42 +0000 |
| commit | 5b445b3844782f4d12de35a6b6a537c265d246d9 (patch) | |
| tree | 8e65f97db1977e5714b0e8f6ce96db353fa70a4a /clang/test/CodeGen/mips-vector-arg.c | |
| parent | df6d7b1564d292a339f07b17c7e38511e589be3d (diff) | |
| download | bcm5719-llvm-5b445b3844782f4d12de35a6b6a537c265d246d9.tar.gz bcm5719-llvm-5b445b3844782f4d12de35a6b6a537c265d246d9.zip | |
[mips] Promote all integral/enumeration types to the GPR width
Summary:
Ensure all integral/enumeration types are appropriately annotated with
signext/zeroext. In particular, i32 now has these attributes when using the
N32/N64 ABI. This paves the way for accurately representing the way the
N32/N64 ABI's promotes integer arguments to i64.
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: cfe-commits, theraven
Differential Revision: http://reviews.llvm.org/D5961
llvm-svn: 220563
Diffstat (limited to 'clang/test/CodeGen/mips-vector-arg.c')
| -rw-r--r-- | clang/test/CodeGen/mips-vector-arg.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/clang/test/CodeGen/mips-vector-arg.c b/clang/test/CodeGen/mips-vector-arg.c index 6ffb0431881..0f23eeaea6a 100644 --- a/clang/test/CodeGen/mips-vector-arg.c +++ b/clang/test/CodeGen/mips-vector-arg.c @@ -8,19 +8,19 @@ typedef float v4sf __attribute__ ((__vector_size__ (16))); typedef int v4i32 __attribute__ ((__vector_size__ (16))); -// O32: define void @test_v4sf(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW:#[0-9]+]] -// O32: declare i32 @test_v4sf_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -// N64: define void @test_v4sf(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW:#[0-9]+]] -// N64: declare i32 @test_v4sf_2(i64, i64, i32, i64, i64, i64) +// O32: define void @test_v4sf(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 signext %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW:#[0-9]+]] +// O32: declare i32 @test_v4sf_2(i32, i32, i32, i32, i32 signext, i32, i32, i32, i32, i32) +// N64: define void @test_v4sf(i64 %a1.coerce0, i64 %a1.coerce1, i32 signext %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW:#[0-9]+]] +// N64: declare i32 @test_v4sf_2(i64, i64, i32 signext, i64, i64, i64) extern test_v4sf_2(v4sf, int, v4sf); void test_v4sf(v4sf a1, int a2, v4sf a3) { test_v4sf_2(a3, a2, a1); } -// O32: define void @test_v4i32(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW]] -// O32: declare i32 @test_v4i32_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -// N64: define void @test_v4i32(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW]] -// N64: declare i32 @test_v4i32_2(i64, i64, i32, i64, i64, i64) +// O32: define void @test_v4i32(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 signext %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW]] +// O32: declare i32 @test_v4i32_2(i32, i32, i32, i32, i32 signext, i32, i32, i32, i32, i32) +// N64: define void @test_v4i32(i64 %a1.coerce0, i64 %a1.coerce1, i32 signext %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW]] +// N64: declare i32 @test_v4i32_2(i64, i64, i32 signext, i64, i64, i64) extern test_v4i32_2(v4i32, int, v4i32); void test_v4i32(v4i32 a1, int a2, v4i32 a3) { test_v4i32_2(a3, a2, a1); |
