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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2015-10-20 11:19:54 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2015-10-20 11:19:54 +0000
commit8bb12d0a77160aa38716f77f15ba6f968765686e (patch)
tree235a524dcf2adabcb6e7669430a589ae77abfe57 /clang/test/CodeGen/builtins-x86.c
parent505f792cbb67ec38083c8d7c7c1d78775a3c5ce8 (diff)
downloadbcm5719-llvm-8bb12d0a77160aa38716f77f15ba6f968765686e.tar.gz
bcm5719-llvm-8bb12d0a77160aa38716f77f15ba6f968765686e.zip
[x86] Fix maskload/store intrinsic definitions in avxintrin.h
According to the Intel documentation, the mask operand of a maskload and maskstore intrinsics is always a vector of packed integer/long integer values. This patch introduces the following two changes: 1. It fixes the avx maskload/store intrinsic definitions in avxintrin.h. 2. It changes BuiltinsX86.def to match the correct gcc definitions for avx maskload/store (see D13861 for more details). Differential Revision: http://reviews.llvm.org/D13861 llvm-svn: 250816
Diffstat (limited to 'clang/test/CodeGen/builtins-x86.c')
-rw-r--r--clang/test/CodeGen/builtins-x86.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/clang/test/CodeGen/builtins-x86.c b/clang/test/CodeGen/builtins-x86.c
index 0721ccb9ff3..83b11a023a2 100644
--- a/clang/test/CodeGen/builtins-x86.c
+++ b/clang/test/CodeGen/builtins-x86.c
@@ -465,14 +465,14 @@ void f0() {
__builtin_ia32_movntdq256(tmp_V4LLip, tmp_V4LLi);
__builtin_ia32_movntpd256(tmp_dp, tmp_V4d);
__builtin_ia32_movntps256(tmp_fp, tmp_V8f);
- tmp_V2d = __builtin_ia32_maskloadpd(tmp_V2dCp, tmp_V2d);
- tmp_V4f = __builtin_ia32_maskloadps(tmp_V4fCp, tmp_V4f);
- tmp_V4d = __builtin_ia32_maskloadpd256(tmp_V4dCp, tmp_V4d);
- tmp_V8f = __builtin_ia32_maskloadps256(tmp_V8fCp, tmp_V8f);
- __builtin_ia32_maskstorepd(tmp_V2dp, tmp_V2d, tmp_V2d);
- __builtin_ia32_maskstoreps(tmp_V4fp, tmp_V4f, tmp_V4f);
- __builtin_ia32_maskstorepd256(tmp_V4dp, tmp_V4d, tmp_V4d);
- __builtin_ia32_maskstoreps256(tmp_V8fp, tmp_V8f, tmp_V8f);
+ tmp_V2d = __builtin_ia32_maskloadpd(tmp_V2dCp, tmp_V2LLi);
+ tmp_V4f = __builtin_ia32_maskloadps(tmp_V4fCp, tmp_V4i);
+ tmp_V4d = __builtin_ia32_maskloadpd256(tmp_V4dCp, tmp_V4LLi);
+ tmp_V8f = __builtin_ia32_maskloadps256(tmp_V8fCp, tmp_V8i);
+ __builtin_ia32_maskstorepd(tmp_V2dp, tmp_V2LLi, tmp_V2d);
+ __builtin_ia32_maskstoreps(tmp_V4fp, tmp_V4i, tmp_V4f);
+ __builtin_ia32_maskstorepd256(tmp_V4dp, tmp_V4LLi, tmp_V4d);
+ __builtin_ia32_maskstoreps256(tmp_V8fp, tmp_V8i, tmp_V8f);
#ifdef USE_3DNOW
tmp_V8c = __builtin_ia32_pavgusb(tmp_V8c, tmp_V8c);
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