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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2019-07-12 18:14:51 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2019-07-12 18:14:51 +0000
commitb98bf60ef7a7ad714b340f980792ec208528cbb2 (patch)
tree6b871f5069ad933efbf96d98ab44b15635f2f533 /clang/test/CodeGen/builtins-systemz-zvector.c
parent0f0a8b77843e73212ab20cc9657b4db7c928abc0 (diff)
downloadbcm5719-llvm-b98bf60ef7a7ad714b340f980792ec208528cbb2.tar.gz
bcm5719-llvm-b98bf60ef7a7ad714b340f980792ec208528cbb2.zip
[SystemZ] Add support for new cpu architecture - arch13
This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10303. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365933
Diffstat (limited to 'clang/test/CodeGen/builtins-systemz-zvector.c')
-rw-r--r--clang/test/CodeGen/builtins-systemz-zvector.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/clang/test/CodeGen/builtins-systemz-zvector.c b/clang/test/CodeGen/builtins-systemz-zvector.c
index f8e5aa3f40d..f814547ee4b 100644
--- a/clang/test/CodeGen/builtins-systemz-zvector.c
+++ b/clang/test/CodeGen/builtins-systemz-zvector.c
@@ -310,6 +310,48 @@ void test_core(void) {
// CHECK: call <2 x i64> @llvm.s390.vpdi(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 5)
// CHECK-ASM: vpdi
+ vss = vec_revb(vss);
+ // CHECK-ASM: vperm
+ vus = vec_revb(vus);
+ // CHECK-ASM: vperm
+ vsi = vec_revb(vsi);
+ // CHECK-ASM: vperm
+ vui = vec_revb(vui);
+ // CHECK-ASM: vperm
+ vsl = vec_revb(vsl);
+ // CHECK-ASM: vperm
+ vul = vec_revb(vul);
+ // CHECK-ASM: vperm
+ vd = vec_revb(vd);
+ // CHECK-ASM: vperm
+
+ vsc = vec_reve(vsc);
+ // CHECK-ASM: vperm
+ vuc = vec_reve(vuc);
+ // CHECK-ASM: vperm
+ vbc = vec_reve(vbc);
+ // CHECK-ASM: vperm
+ vss = vec_reve(vss);
+ // CHECK-ASM: vperm
+ vus = vec_reve(vus);
+ // CHECK-ASM: vperm
+ vbs = vec_reve(vbs);
+ // CHECK-ASM: vperm
+ vsi = vec_reve(vsi);
+ // CHECK-ASM: vperm
+ vui = vec_reve(vui);
+ // CHECK-ASM: vperm
+ vbi = vec_reve(vbi);
+ // CHECK-ASM: vperm
+ vsl = vec_reve(vsl);
+ // CHECK-ASM: {{vperm|vpdi}}
+ vul = vec_reve(vul);
+ // CHECK-ASM: {{vperm|vpdi}}
+ vbl = vec_reve(vbl);
+ // CHECK-ASM: {{vperm|vpdi}}
+ vd = vec_reve(vd);
+ // CHECK-ASM: {{vperm|vpdi}}
+
vsc = vec_sel(vsc, vsc, vuc);
// CHECK-ASM: vsel
vsc = vec_sel(vsc, vsc, vbc);
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