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authorTony Jiang <jtony@ca.ibm.com>2017-01-11 20:59:42 +0000
committerTony Jiang <jtony@ca.ibm.com>2017-01-11 20:59:42 +0000
commit974e4c78999ad00af0505a9bf50b7432b219f717 (patch)
tree457f2551e77e75a4543769a1b76f56c2b539ae11 /clang/test/CodeGen/builtins-ppc-p9vector.c
parent83962656557bdea5499ec022094fd6c60c1db389 (diff)
downloadbcm5719-llvm-974e4c78999ad00af0505a9bf50b7432b219f717.tar.gz
bcm5719-llvm-974e4c78999ad00af0505a9bf50b7432b219f717.zip
[PowerPC] Fix the wrong implementation of builtin vec_rlnm.
llvm-svn: 291702
Diffstat (limited to 'clang/test/CodeGen/builtins-ppc-p9vector.c')
-rw-r--r--clang/test/CodeGen/builtins-ppc-p9vector.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/clang/test/CodeGen/builtins-ppc-p9vector.c b/clang/test/CodeGen/builtins-ppc-p9vector.c
index bd0ad182f15..42316970d8d 100644
--- a/clang/test/CodeGen/builtins-ppc-p9vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p9vector.c
@@ -868,20 +868,24 @@ vector unsigned long long test76(void) {
return vec_rlmi(vula, vula, vula);
}
vector unsigned int test77(void) {
+// CHECK-BE: %[[RES1:.+]] = shl <4 x i32
+// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
// CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
-// CHECK-BE: and <4 x i32
// CHECK-BE: ret <4 x i32>
+// CHECK: %[[RES1:.+]] = shl <4 x i32
+// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
// CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
-// CHECK: and <4 x i32
// CHECK: ret <4 x i32>
return vec_rlnm(vuia, vuia, vuia);
}
vector unsigned long long test78(void) {
+// CHECK-BE: %[[RES1:.+]] = shl <2 x i64
+// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
// CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
-// CHECK-BE: and <2 x i64
// CHECK-BE-NEXT: ret <2 x i64>
+// CHECK: %[[RES1:.+]] = shl <2 x i64
+// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
// CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
-// CHECK: and <2 x i64
// CHECK-NEXT: ret <2 x i64>
return vec_rlnm(vula, vula, vula);
}
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