[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi

My original LE implementation of the vsldoi instruction, with its
altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect
shufflevector operations in the LLVM IR.  Correct code is generated
because the back end handles the incorrect shufflevector in a
consistent manner.

This patch and a companion patch for LLVM correct this problem by
removing the fixup from altivec.h and the corresponding fixup from the
PowerPC back end.  Several test cases are also modified to reflect the
now-correct LLVM IR.

The vec_sums and vec_vsumsws interfaces in altivec.h are also fixed,
because they used vec_perm calls intended to be recognized as vsldoi
instructions.  These vec_perm calls are now replaced with code that
more clearly shows the intent of the transformation.

llvm-svn: 214801

1 files changed, 0 insertions, 34 deletions

diff --git a/clang/test/CodeGen/builtins-ppc-altivec.c b/clang/test/CodeGen/builtins-ppc-altivec.c
index 50225c224ec..c6aa3c2faac 100644
--- a/clang/test/CodeGen/builtins-ppc-altivec.c
+++ b/clang/test/CodeGen/builtins-ppc-altivec.c
@@ -3258,98 +3258,66 @@ void test6() {
   /* vec_sld */
   res_vsc = vec_sld(vsc, vsc, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vuc = vec_sld(vuc, vuc, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vs  = vec_sld(vs, vs, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vus = vec_sld(vus, vus, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vp  = vec_sld(vp, vp, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vi  = vec_sld(vi, vi, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vui = vec_sld(vui, vui, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vf  = vec_sld(vf, vf, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vsc = vec_vsldoi(vsc, vsc, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vuc = vec_vsldoi(vuc, vuc, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vs  = vec_vsldoi(vs, vs, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vus = vec_vsldoi(vus, vus, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vp  = vec_vsldoi(vp, vp, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vi  = vec_vsldoi(vi, vi, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vui = vec_vsldoi(vui, vui, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vf  = vec_vsldoi(vf, vf, 0);
 // CHECK: @llvm.ppc.altivec.vperm
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 1
-// CHECK-LE: sub nsw i32 {{[%_.a-z0-9]+}}, 15
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   /* vec_sll */
@@ -5189,13 +5157,11 @@ void test6() {
 // CHECK: @llvm.ppc.altivec.vsumsws
 // CHECK-LE: @llvm.ppc.altivec.vperm
 // CHECK-LE: @llvm.ppc.altivec.vsumsws
-// CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vi = vec_vsumsws(vi, vi);
 // CHECK: @llvm.ppc.altivec.vsumsws
 // CHECK-LE: @llvm.ppc.altivec.vperm
 // CHECK-LE: @llvm.ppc.altivec.vsumsws
-// CHECK-LE: @llvm.ppc.altivec.vperm
 
   /* vec_trunc */
   res_vf = vec_trunc(vf);