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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-29 13:54:31 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-29 13:54:31 +0000 |
commit | 790e422be9e0e9b1e8de250819fcfae84ae6e42c (patch) | |
tree | f9099c88d5113443150a39e6c2d96fadaa06ef84 /clang/test/CodeGen/builtins-hexagon.c | |
parent | 0f08dff1b569b1285992644fe783fc67c39a4209 (diff) | |
download | bcm5719-llvm-790e422be9e0e9b1e8de250819fcfae84ae6e42c.tar.gz bcm5719-llvm-790e422be9e0e9b1e8de250819fcfae84ae6e42c.zip |
[Hexagon] Aid bit-reverse load intrinsics lowering with bitcode
The conversion of operatios to bitcode helps to eliminate an additional
store in certain cases. We used to lower these load intrinsics in DAG to
DAG conversion by which time, the "Dead Store Elimination" pass is
already run. There is an associated LLVM patch.
Patch by Sumanth Gundapaneni.
llvm-svn: 328776
Diffstat (limited to 'clang/test/CodeGen/builtins-hexagon.c')
-rw-r--r-- | clang/test/CodeGen/builtins-hexagon.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/clang/test/CodeGen/builtins-hexagon.c b/clang/test/CodeGen/builtins-hexagon.c index 22835a23f29..3b4d8d057a0 100644 --- a/clang/test/CodeGen/builtins-hexagon.c +++ b/clang/test/CodeGen/builtins-hexagon.c @@ -3322,28 +3322,30 @@ void test() { __builtin_HEXAGON_Y4_l2fetch(0, 0); // CHECK: @llvm.hexagon.Y5.l2fetch __builtin_HEXAGON_Y5_l2fetch(0, 0); - // CHECK: @llvm.hexagon.brev.ldb + + // CHECK: @llvm.hexagon.L2.loadrb.pbr __builtin_brev_ldb(0, 0, 0); - // CHECK: @llvm.hexagon.brev.ldd + // CHECK: @llvm.hexagon.L2.loadrd.pbr __builtin_brev_ldd(0, 0, 0); - // CHECK: @llvm.hexagon.brev.ldh + // CHECK: @llvm.hexagon.L2.loadrh.pbr __builtin_brev_ldh(0, 0, 0); - // CHECK: @llvm.hexagon.brev.ldub + // CHECK: @llvm.hexagon.L2.loadrub.pbr __builtin_brev_ldub(0, 0, 0); - // CHECK: @llvm.hexagon.brev.lduh + // CHECK: @llvm.hexagon.L2.loadruh.pbr __builtin_brev_lduh(0, 0, 0); - // CHECK: @llvm.hexagon.brev.ldw + // CHECK: @llvm.hexagon.L2.loadri.pbr __builtin_brev_ldw(0, 0, 0); - // CHECK: @llvm.hexagon.brev.stb + // CHECK: @llvm.hexagon.S2.storerb.pbr __builtin_brev_stb(0, 0, 0); - // CHECK: @llvm.hexagon.brev.std - __builtin_brev_std(0, 0, 0); - // CHECK: @llvm.hexagon.brev.sth + // CHECK: @llvm.hexagon.S2.storerd.pbr + __builtin_brev_std(0, 0LL, 0); + // CHECK: @llvm.hexagon.S2.storerh.pbr __builtin_brev_sth(0, 0, 0); - // CHECK: @llvm.hexagon.brev.sthhi + // CHECK: @llvm.hexagon.S2.storerf.pbr __builtin_brev_sthhi(0, 0, 0); - // CHECK: @llvm.hexagon.brev.stw + // CHECK: @llvm.hexagon.S2.storeri.pbr __builtin_brev_stw(0, 0, 0); + // CHECK: @llvm.hexagon.circ.ldb __builtin_circ_ldb(0, 0, 0, 0); // CHECK: @llvm.hexagon.circ.ldd |