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| author | Reid Kleckner <rnk@google.com> | 2018-06-07 21:39:04 +0000 |
|---|---|---|
| committer | Reid Kleckner <rnk@google.com> | 2018-06-07 21:39:04 +0000 |
| commit | aa46ed92786077ae0b779372d52a73085965c1c8 (patch) | |
| tree | 1fbd403a7497794cbab3c61bf31112f1573a9bc8 /clang/test/CodeGen/bittest-intrin.c | |
| parent | 1ca21bb5e654088b6263ed48a137ec2d61faeb8e (diff) | |
| download | bcm5719-llvm-aa46ed92786077ae0b779372d52a73085965c1c8.tar.gz bcm5719-llvm-aa46ed92786077ae0b779372d52a73085965c1c8.zip | |
[MS] Re-add support for the ARM interlocked bittest intrinscs
Adds support for these intrinsics, which are ARM and ARM64 only:
_interlockedbittestandreset_acq
_interlockedbittestandreset_rel
_interlockedbittestandreset_nf
_interlockedbittestandset_acq
_interlockedbittestandset_rel
_interlockedbittestandset_nf
Refactor the bittest intrinsic handling to decompose each intrinsic into
its action, its width, and its atomicity.
llvm-svn: 334239
Diffstat (limited to 'clang/test/CodeGen/bittest-intrin.c')
| -rw-r--r-- | clang/test/CodeGen/bittest-intrin.c | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/clang/test/CodeGen/bittest-intrin.c b/clang/test/CodeGen/bittest-intrin.c index 21a26efa107..f89a8267b0c 100644 --- a/clang/test/CodeGen/bittest-intrin.c +++ b/clang/test/CodeGen/bittest-intrin.c @@ -10,7 +10,9 @@ void test32(long *base, long idx) { sink = _bittestandset(base, idx); sink = _interlockedbittestandreset(base, idx); sink = _interlockedbittestandset(base, idx); + sink = _interlockedbittestandset(base, idx); } + void test64(__int64 *base, __int64 idx) { sink = _bittest64(base, idx); sink = _bittestandcomplement64(base, idx); @@ -20,6 +22,17 @@ void test64(__int64 *base, __int64 idx) { sink = _interlockedbittestandset64(base, idx); } +#if defined(_M_ARM) || defined(_M_ARM64) +void test_arm(long *base, long idx) { + sink = _interlockedbittestandreset_acq(base, idx); + sink = _interlockedbittestandreset_rel(base, idx); + sink = _interlockedbittestandreset_nf(base, idx); + sink = _interlockedbittestandset_acq(base, idx); + sink = _interlockedbittestandset_rel(base, idx); + sink = _interlockedbittestandset_nf(base, idx); +} +#endif + // X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx) // X64: call i8 asm sideeffect "btl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{{.*}}"(i32* %{{.*}}, i32 {{.*}}) // X64: call i8 asm sideeffect "btcl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{{.*}}"(i32* %{{.*}}, i32 {{.*}}) @@ -110,15 +123,13 @@ void test64(__int64 *base, __int64 idx) { // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1 // ARM: store volatile i8 %[[RES]], i8* @sink, align 1 -// ARM-LABEL: define dso_local {{.*}}void @test64(i64* %base, i64 %idx) -// ARM: %[[IDXHI:[^ ]*]] = ashr i64 %{{.*}}, 3 -// ARM: %[[BASE:[^ ]*]] = bitcast i64* %{{.*}} to i8* -// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i64 %[[IDXHI]] -// ARM: %[[IDX8:[^ ]*]] = trunc i64 %{{.*}} to i8 -// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7 -// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1 -// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]] -// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1 -// ARM: store volatile i8 %[[RES]], i8* @sink, align 1 -// ... the rest is the same, but with i64 instead of i32. +// Just look for the atomicrmw instructions. + +// ARM-LABEL: define dso_local {{.*}}void @test_arm(i32* %base, i32 %idx) +// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} acquire +// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} release +// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} monotonic +// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} acquire +// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} release +// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} monotonic |
