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author | Richard Trieu <rtrieu@google.com> | 2013-01-31 01:44:26 +0000 |
---|---|---|
committer | Richard Trieu <rtrieu@google.com> | 2013-01-31 01:44:26 +0000 |
commit | de5cc7d3d87eb654f11af27387279a3daf9d7382 (patch) | |
tree | d1943193b90683f81ea178ba93c3e6493a8eef61 /clang/test/CodeGen/bitfield-2.c | |
parent | 3ea7fc62ef388f0909c7fd2cdacd79a055f9518b (diff) | |
download | bcm5719-llvm-de5cc7d3d87eb654f11af27387279a3daf9d7382.tar.gz bcm5719-llvm-de5cc7d3d87eb654f11af27387279a3daf9d7382.zip |
Add indents to AST dumping and removed parenthesis from AST nodes.
Indents were given the color blue when outputting with color.
AST dumping now looks like this:
Node
|-Node
| `-Node
`-Node
`-Node
Compared to the previous:
(Node
(Node
(Node))
(Node
(Node)))
llvm-svn: 174022
Diffstat (limited to 'clang/test/CodeGen/bitfield-2.c')
-rw-r--r-- | clang/test/CodeGen/bitfield-2.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/clang/test/CodeGen/bitfield-2.c b/clang/test/CodeGen/bitfield-2.c index 867ed8c2cec..bec55ffa751 100644 --- a/clang/test/CodeGen/bitfield-2.c +++ b/clang/test/CodeGen/bitfield-2.c @@ -9,7 +9,7 @@ // PR6176 // CHECK-RECORD: *** Dumping IRgen Record Layout -// CHECK-RECORD: Record: (RecordDecl{{.*}}s0 +// CHECK-RECORD: Record: RecordDecl{{.*}}s0 // CHECK-RECORD: Layout: <CGRecordLayout // CHECK-RECORD: LLVMType:%struct.s0 = type <{ [3 x i8] }> // CHECK-RECORD: IsZeroInitializable:1 @@ -49,7 +49,7 @@ unsigned long long test_0() { // PR5591 // CHECK-RECORD: *** Dumping IRgen Record Layout -// CHECK-RECORD: Record: (RecordDecl{{.*}}s1 +// CHECK-RECORD: Record: RecordDecl{{.*}}s1 // CHECK-RECORD: Layout: <CGRecordLayout // CHECK-RECORD: LLVMType:%struct.s1 = type <{ [3 x i8] }> // CHECK-RECORD: IsZeroInitializable:1 @@ -97,7 +97,7 @@ unsigned long long test_1() { // PR5567 // CHECK-RECORD: *** Dumping IRgen Record Layout -// CHECK-RECORD: Record: (RecordDecl{{.*}}u2 +// CHECK-RECORD: Record: RecordDecl{{.*}}u2 // CHECK-RECORD: Layout: <CGRecordLayout // CHECK-RECORD: LLVMType:%union.u2 = type <{ i8 }> // CHECK-RECORD: IsZeroInitializable:1 @@ -269,7 +269,7 @@ _Bool test_6() { // Check that we compute the best alignment possible for each access. // // CHECK-RECORD: *** Dumping IRgen Record Layout -// CHECK-RECORD: Record: (RecordDecl{{.*}}s7 +// CHECK-RECORD: Record: RecordDecl{{.*}}s7 // CHECK-RECORD: Layout: <CGRecordLayout // CHECK-RECORD: LLVMType:%struct.s7 = type { i32, i32, i32, i8, [3 x i8], [4 x i8], [12 x i8] } // CHECK-RECORD: IsZeroInitializable:1 |