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author | Eric Christopher <echristo@gmail.com> | 2015-10-08 20:10:18 +0000 |
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committer | Eric Christopher <echristo@gmail.com> | 2015-10-08 20:10:18 +0000 |
commit | a7260af7e51e8ebc9b3b4ea1e6ffb9c61a92d181 (patch) | |
tree | ddf5295983c7af58341decd3b37763894d6696ab /clang/test/CodeGen/attr-target-x86.c | |
parent | bbd746db9ed5b52ea00a1ec72ee67f15660e0921 (diff) | |
download | bcm5719-llvm-a7260af7e51e8ebc9b3b4ea1e6ffb9c61a92d181.tar.gz bcm5719-llvm-a7260af7e51e8ebc9b3b4ea1e6ffb9c61a92d181.zip |
Handle sse turning on mmx, but no -mmx not turning off SSE.
Rationale :
// sse3
__m128d test_mm_addsub_pd(__m128d A, __m128d B) {
return _mm_addsub_pd(A, B);
}
// mmx
void shift(__m64 a, __m64 b, int c) {
_mm_slli_pi16(a, c);
_mm_slli_pi32(a, c);
_mm_slli_si64(a, c);
_mm_srli_pi16(a, c);
_mm_srli_pi32(a, c);
_mm_srli_si64(a, c);
_mm_srai_pi16(a, c);
_mm_srai_pi32(a, c);
}
clang -msse3 -mno-mmx file.c -c
For this code we should be able to explicitly turn off MMX
without affecting the compilation of the SSE3 function and then
diagnose and error on compiling the MMX function.
This is a preparatory patch to the actual diagnosis code which is
coming in a future patch. This sets us up to have the correct information
where we need it and verifies that it's being emitted for the backend
to handle.
llvm-svn: 249733
Diffstat (limited to 'clang/test/CodeGen/attr-target-x86.c')
-rw-r--r-- | clang/test/CodeGen/attr-target-x86.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c index 5f762ff9719..e0403ee2d3e 100644 --- a/clang/test/CodeGen/attr-target-x86.c +++ b/clang/test/CodeGen/attr-target-x86.c @@ -16,6 +16,8 @@ int bar(int a) { return baz(a) + foo(a); } int __attribute__((target("avx, sse4.2, arch= ivybridge"))) qux(int a) { return 4; } int __attribute__((target("no-aes, arch=ivybridge"))) qax(int a) { return 4; } +int __attribute__((target("no-mmx"))) qq(int a) { return 40; } + // Check that we emit the additional subtarget and cpu features for foo and not for baz or bar. // CHECK: baz{{.*}} #0 // CHECK: foo{{.*}} #1 @@ -28,8 +30,10 @@ int __attribute__((target("no-aes, arch=ivybridge"))) qax(int a) { return 4; } // CHECK: bar{{.*}} #0 // CHECK: qux{{.*}} #1 // CHECK: qax{{.*}} #4 -// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2" -// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" -// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop" -// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" -// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,-aes" +// CHECK: qq{{.*}} #5 +// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2" +// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" +// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop" +// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" +// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,-aes" +// CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2,-3dnow,-3dnowa,-mmx" |