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| author | JF Bastien <jfbastien@apple.com> | 2019-07-25 16:11:57 +0000 |
|---|---|---|
| committer | JF Bastien <jfbastien@apple.com> | 2019-07-25 16:11:57 +0000 |
| commit | dbc0a5df8d5f4fb826325b4f169acb5c26250c87 (patch) | |
| tree | a878ee10aaf8b7dd71338eee927006dbc251dc44 /clang/test/CodeGen/arm_acle.c | |
| parent | eb3c1ca896fa858f421c6247d1a5a30edad9535f (diff) | |
| download | bcm5719-llvm-dbc0a5df8d5f4fb826325b4f169acb5c26250c87.tar.gz bcm5719-llvm-dbc0a5df8d5f4fb826325b4f169acb5c26250c87.zip | |
Allow prefetching from non-zero address spaces
Summary:
This is useful for targets which have prefetch instructions for non-default address spaces.
<rdar://problem/42662136>
Subscribers: nemanjai, javed.absar, hiraditya, kbarton, jkorous, dexonsmith, cfe-commits, llvm-commits, RKSimon, hfinkel, t.p.northover, craig.topper, anemet
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D65254
llvm-svn: 367032
Diffstat (limited to 'clang/test/CodeGen/arm_acle.c')
| -rw-r--r-- | clang/test/CodeGen/arm_acle.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c index beca9373506..2f086ee70bf 100644 --- a/clang/test/CodeGen/arm_acle.c +++ b/clang/test/CodeGen/arm_acle.c @@ -88,28 +88,28 @@ void test_swp(uint32_t x, volatile void *p) { /* 8.6 Memory prefetch intrinsics */ /* 8.6.1 Data prefetch */ // ARM-LABEL: test_pld -// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 1) +// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 1) void test_pld() { __pld(0); } // ARM-LABEL: test_pldx -// AArch32: call void @llvm.prefetch(i8* null, i32 1, i32 3, i32 1) -// AArch64: call void @llvm.prefetch(i8* null, i32 1, i32 1, i32 1) +// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 3, i32 1) +// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1) void test_pldx() { __pldx(1, 2, 0, 0); } /* 8.6.2 Instruction prefetch */ // ARM-LABEL: test_pli -// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) +// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0) void test_pli() { __pli(0); } // ARM-LABEL: test_plix -// AArch32: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) -// AArch64: call void @llvm.prefetch(i8* null, i32 0, i32 1, i32 0) +// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0) +// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 1, i32 0) void test_plix() { __plix(2, 0, 0); } |
