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| author | Craig Topper <craig.topper@intel.com> | 2018-10-24 17:42:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-10-24 17:42:17 +0000 |
| commit | 3113ec3dc78e027fcfeef54a62d117c9d566d4f1 (patch) | |
| tree | d21d09bba9f9e202f5b3395f55b2e244c490139b /clang/test/CodeGen/arm64_vdupq_n_f64.c | |
| parent | 618c0bc363033a2a9d4a3f2b1a0c09c4703e4e55 (diff) | |
| download | bcm5719-llvm-3113ec3dc78e027fcfeef54a62d117c9d566d4f1.tar.gz bcm5719-llvm-3113ec3dc78e027fcfeef54a62d117c9d566d4f1.zip | |
[CodeGen] Update min-legal-vector width based on function argument and return types
This is a continuation of my patches to inform the X86 backend about what the largest IR types are in the function so that we can restrict the backend type legalizer to prevent 512-bit vectors on SKX when -mprefer-vector-width=256 is specified if no explicit 512 bit vectors were specified by the user.
This patch updates the vector width based on the argument and return types of the current function and from the types of any functions it calls. This is intended to make sure the backend type legalizer doesn't disturb any types that are required for ABI.
Differential Revision: https://reviews.llvm.org/D52441
llvm-svn: 345168
Diffstat (limited to 'clang/test/CodeGen/arm64_vdupq_n_f64.c')
| -rw-r--r-- | clang/test/CodeGen/arm64_vdupq_n_f64.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/clang/test/CodeGen/arm64_vdupq_n_f64.c b/clang/test/CodeGen/arm64_vdupq_n_f64.c index e9e814e92a0..24c57c4f0de 100644 --- a/clang/test/CodeGen/arm64_vdupq_n_f64.c +++ b/clang/test/CodeGen/arm64_vdupq_n_f64.c @@ -44,7 +44,7 @@ float64x2_t test_vmovq_n_f64(float64_t w) { return vmovq_n_f64(w); } -// CHECK-LABEL: define <4 x half> @test_vmov_n_f16(half* %a1) #0 { +// CHECK-LABEL: define <4 x half> @test_vmov_n_f16(half* %a1) #1 { // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 // CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0 // CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1 @@ -76,3 +76,5 @@ float16x8_t test_vmovq_n_f16(float16_t *a1) { return vmovq_n_f16(*a1); } +// CHECK: attributes #0 ={{.*}}"min-legal-vector-width"="128" +// CHECK: attributes #1 ={{.*}}"min-legal-vector-width"="64" |
