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authorTim Northover <tnorthover@apple.com>2014-03-29 15:09:45 +0000
committerTim Northover <tnorthover@apple.com>2014-03-29 15:09:45 +0000
commita2ee433c8d99632419d4a13a66cc4d06eada4014 (patch)
treee6ab2db8facbc4c5ed2fb11df260db8138572ace /clang/test/CodeGen/arm64_vcvtfp.c
parentaf3698066a1ea2e5ab4cc08ae9a59620cf18adb7 (diff)
downloadbcm5719-llvm-a2ee433c8d99632419d4a13a66cc4d06eada4014.tar.gz
bcm5719-llvm-a2ee433c8d99632419d4a13a66cc4d06eada4014.zip
ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
Diffstat (limited to 'clang/test/CodeGen/arm64_vcvtfp.c')
-rw-r--r--clang/test/CodeGen/arm64_vcvtfp.c48
1 files changed, 48 insertions, 0 deletions
diff --git a/clang/test/CodeGen/arm64_vcvtfp.c b/clang/test/CodeGen/arm64_vcvtfp.c
new file mode 100644
index 00000000000..030fe772e42
--- /dev/null
+++ b/clang/test/CodeGen/arm64_vcvtfp.c
@@ -0,0 +1,48 @@
+// RUN: %clang -O1 -target arm64-apple-ios7 -ffreestanding -S -o - -emit-llvm %s | FileCheck %s
+
+#include <arm_neon.h>
+
+float64x2_t test_vcvt_f64_f32(float32x2_t x) {
+ // CHECK-LABEL: test_vcvt_f64_f32
+ return vcvt_f64_f32(x);
+ // CHECK: fpext <2 x float> {{%.*}} to <2 x double>
+ // CHECK-NEXT: ret
+}
+
+float64x2_t test_vcvt_high_f64_f32(float32x4_t x) {
+ // CHECK-LABEL: test_vcvt_high_f64_f32
+ return vcvt_high_f64_f32(x);
+ // CHECK: [[HIGH:%.*]] = shufflevector <4 x float> {{%.*}}, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+ // CHECK-NEXT: fpext <2 x float> [[HIGH]] to <2 x double>
+ // CHECK-NEXT: ret
+}
+
+float32x2_t test_vcvt_f32_f64(float64x2_t v) {
+ // CHECK: test_vcvt_f32_f64
+ return vcvt_f32_f64(v);
+ // CHECK: fptrunc <2 x double> {{%.*}} to <2 x float>
+ // CHECK-NEXT: ret
+}
+
+float32x4_t test_vcvt_high_f32_f64(float32x2_t x, float64x2_t v) {
+ // CHECK: test_vcvt_high_f32_f64
+ return vcvt_high_f32_f64(x, v);
+ // CHECK: [[TRUNC:%.*]] = fptrunc <2 x double> {{.*}} to <2 x float>
+ // CHECK-NEXT: shufflevector <2 x float> {{.*}}, <2 x float> [[TRUNC]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ // CHECK-NEXT: ret
+}
+
+float32x2_t test_vcvtx_f32_f64(float64x2_t v) {
+ // CHECK: test_vcvtx_f32_f64
+ return vcvtx_f32_f64(v);
+ // CHECK: llvm.arm64.neon.fcvtxn.v2f32.v2f64
+ // CHECK-NEXT: ret
+}
+
+float32x4_t test_vcvtx_high_f32_f64(float32x2_t x, float64x2_t v) {
+ // CHECK: test_vcvtx_high_f32_f64
+ return vcvtx_high_f32_f64(x, v);
+ // CHECK: llvm.arm64.neon.fcvtxn.v2f32.v2f64
+ // CHECK: shufflevector
+ // CHECK-NEXT: ret
+}
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