ARM64: track alignment padding registers on AAPCS targets

This implements clause C.8 of the AAPCS in the front-end, so that Clang
accurately knows when the registers run out and it has to insert padding before
the stack objects begin.

PR19432.

llvm-svn: 206296

1 files changed, 14 insertions, 0 deletions

diff --git a/clang/test/CodeGen/arm64-aapcs-arguments.c b/clang/test/CodeGen/arm64-aapcs-arguments.c
new file mode 100644
index 00000000000..283296c4ca4
--- /dev/null
+++ b/clang/test/CodeGen/arm64-aapcs-arguments.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple arm64-linux-gnu -target-abi aapcs -ffreestanding -emit-llvm -w -o - %s | FileCheck %s
+
+// AAPCS clause C.8 says: If the argument has an alignment of 16 then the NGRN
+// is rounded up to the next even number.
+
+// CHECK: void @test1(i32 %x0, i128 %x2_x3, i128 %x4_x5, i128 %x6_x7, i128 %sp.coerce)
+typedef union { __int128 a; } Small;
+void test1(int x0, __int128 x2_x3, __int128 x4_x5, __int128 x6_x7, Small sp) {
+}
+
+
+// CHECK: void @test2(i32 %x0, i128 %x2_x3.coerce, i32 %x4, i128 %x6_x7.coerce, i32 %sp, i128 %sp16.coerce)
+void test2(int x0, Small x2_x3, int x4, Small x6_x7, int sp, Small sp16) {
+}