[ARM] Support inline assembler constraints for MVE.

"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.

Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60709

llvm-svn: 364331

1 files changed, 18 insertions, 0 deletions

diff --git a/clang/test/CodeGen/arm-asm.c b/clang/test/CodeGen/arm-asm.c
index bd2fe119936..d2ae1ed7623 100644
--- a/clang/test/CodeGen/arm-asm.c
+++ b/clang/test/CodeGen/arm-asm.c
@@ -6,3 +6,21 @@ int t1() {
     __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv" (k) : "s15");
     return 0;
 }
+
+// CHECK-LABEL: @even_reg_constraint_Te
+int even_reg_constraint_Te(void) {
+  int acc = 0;
+  // CHECK: vaddv{{.*\^Te}}
+  asm("vaddv.s8 %0, Q0"
+      : "+Te" (acc));
+  return acc;
+}
+
+// CHECK-LABEL: @odd_reg_constraint_To
+int odd_reg_constraint_To(void) {
+  int eacc = 0, oacc = 0;
+  // CHECK: vaddlv{{.*\^To}}
+  asm("vaddlv.s8 %0, %1, Q0"
+      : "+Te" (eacc), "+To" (oacc));
+  return oacc;
+}