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| author | Javed Absar <javed.absar@arm.com> | 2017-05-30 10:12:15 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2017-05-30 10:12:15 +0000 |
| commit | 3d92d7ab36e23b1de25c1bfca16c166df54d1fb2 (patch) | |
| tree | 5c1c45ba5c0111dada7aa4e1bf4d31deccf05444 /clang/test/CodeGen/arm-abi-vector.c | |
| parent | 6ceea9a4d38031155fad4243bdb26904c0b1c349 (diff) | |
| download | bcm5719-llvm-3d92d7ab36e23b1de25c1bfca16c166df54d1fb2.tar.gz bcm5719-llvm-3d92d7ab36e23b1de25c1bfca16c166df54d1fb2.zip | |
[ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205
llvm-svn: 304201
Diffstat (limited to 'clang/test/CodeGen/arm-abi-vector.c')
| -rw-r--r-- | clang/test/CodeGen/arm-abi-vector.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/clang/test/CodeGen/arm-abi-vector.c b/clang/test/CodeGen/arm-abi-vector.c index 8d113d6533e..4e6a9720303 100644 --- a/clang/test/CodeGen/arm-abi-vector.c +++ b/clang/test/CodeGen/arm-abi-vector.c @@ -133,20 +133,20 @@ double test_5c(__char5 *in) { double varargs_vec_9c(int fixed, ...) { // CHECK: varargs_vec_9c -// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16 +// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8 // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* // CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16 // CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>* // CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8 -// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16 +// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8 // APCS-GNU: varargs_vec_9c -// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16 +// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8 // APCS-GNU: [[AP:%.*]] = load i8*, // APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16 // APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>* // APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4 -// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16 +// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8 // ANDROID: varargs_vec_9c // ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16 // ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 @@ -246,15 +246,15 @@ double test_3s(__short3 *in) { double varargs_vec_5s(int fixed, ...) { // CHECK: varargs_vec_5s -// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 16 +// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 8 // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* // CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16 // CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <5 x i16>* // CHECK: [[VEC:%.*]] = load <5 x i16>, <5 x i16>* [[AP_CAST]], align 8 -// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 16 +// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 8 // APCS-GNU: varargs_vec_5s -// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 16 +// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 8 // APCS-GNU: [[AP:%.*]] = load i8*, // APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16 // APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <5 x i16>* |
