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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-07 16:25:22 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-07 16:25:22 +0000 |
| commit | d240953db24441c69b89803c95c7f6a3e9806c14 (patch) | |
| tree | 4b994f70cfa1d04f6064fdf73062c55a33de94e2 /clang/test/ASTMerge/Inputs/exprs1.c | |
| parent | 602bff3184d5870167ee1a1e345f420a8b093c05 (diff) | |
| download | bcm5719-llvm-d240953db24441c69b89803c95c7f6a3e9806c14.tar.gz bcm5719-llvm-d240953db24441c69b89803c95c7f6a3e9806c14.zip | |
[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).
The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.
Reviewers: vmedic
Subscribers: emaste, llvm-commits
Differential Revision: http://reviews.llvm.org/D3569
llvm-svn: 208221
Diffstat (limited to 'clang/test/ASTMerge/Inputs/exprs1.c')
0 files changed, 0 insertions, 0 deletions
