summaryrefslogtreecommitdiffstats
path: root/clang/lib
diff options
context:
space:
mode:
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-07-21 18:07:15 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-07-21 18:07:15 +0000
commit33e67ad098e3e3cb5e2565decaaac85123d7f004 (patch)
tree9b18ebf6c1556b3828f5f2e1fcabcf4ecfd763b7 /clang/lib
parent37a58e03c72df95398807aab8c44b95b91146705 (diff)
downloadbcm5719-llvm-33e67ad098e3e3cb5e2565decaaac85123d7f004.tar.gz
bcm5719-llvm-33e67ad098e3e3cb5e2565decaaac85123d7f004.zip
[Hexagon] Add inline-asm constraint 'a' for modifier register class
For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308763
Diffstat (limited to 'clang/lib')
-rw-r--r--clang/lib/Basic/Targets.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 01137b66b38..d488ed1dbd7 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -6887,6 +6887,9 @@ public:
return true;
}
break;
+ case 'a': // Modifier register m0-m1.
+ Info.setAllowsRegister();
+ return true;
case 's':
// Relocatable constant.
return true;
OpenPOWER on IntegriCloud