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authorCraig Topper <craig.topper@intel.com>2018-08-14 20:21:05 +0000
committerCraig Topper <craig.topper@intel.com>2018-08-14 20:21:05 +0000
commit2a87314e75a47796186a7e846802d2bde4cb63c1 (patch)
tree6baca0024a5c07a1ce88f75e7102bf2466c164ce /clang/lib
parent97e6819e79b6ba5df3f46c251c6d3c2ff1c1d78d (diff)
downloadbcm5719-llvm-2a87314e75a47796186a7e846802d2bde4cb63c1.tar.gz
bcm5719-llvm-2a87314e75a47796186a7e846802d2bde4cb63c1.zip
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly
Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
Diffstat (limited to 'clang/lib')
-rw-r--r--clang/lib/CodeGen/CGStmt.cpp14
1 files changed, 14 insertions, 0 deletions
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 4eff1ca0811..09c322a8529 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -1979,6 +1979,11 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
diag::err_asm_invalid_type_in_input)
<< OutExpr->getType() << OutputConstraint;
}
+
+ // Update largest vector width for any vector types.
+ if (auto *VT = dyn_cast<llvm::VectorType>(ResultRegTypes.back()))
+ LargestVectorWidth = std::max(LargestVectorWidth,
+ VT->getPrimitiveSizeInBits());
} else {
ArgTypes.push_back(Dest.getAddress().getType());
Args.push_back(Dest.getPointer());
@@ -2000,6 +2005,10 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
Arg->getType()))
Arg = Builder.CreateBitCast(Arg, AdjTy);
+ // Update largest vector width for any vector types.
+ if (auto *VT = dyn_cast<llvm::VectorType>(Arg->getType()))
+ LargestVectorWidth = std::max(LargestVectorWidth,
+ VT->getPrimitiveSizeInBits());
if (Info.allowsRegister())
InOutConstraints += llvm::utostr(i);
else
@@ -2080,6 +2089,11 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
CGM.getDiags().Report(S.getAsmLoc(), diag::err_asm_invalid_type_in_input)
<< InputExpr->getType() << InputConstraint;
+ // Update largest vector width for any vector types.
+ if (auto *VT = dyn_cast<llvm::VectorType>(Arg->getType()))
+ LargestVectorWidth = std::max(LargestVectorWidth,
+ VT->getPrimitiveSizeInBits());
+
ArgTypes.push_back(Arg->getType());
Args.push_back(Arg);
Constraints += InputConstraint;
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