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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-26 18:19:28 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-26 18:19:28 +0000 |
| commit | f33d9052935869fb2b70272b41de5b5df610c958 (patch) | |
| tree | 1e64db3a3965e27f5a8590916780b04426b7c0f8 /clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | |
| parent | 7c4b5d92f14ac38eaae17f5e486c83bcdc87344b (diff) | |
| download | bcm5719-llvm-f33d9052935869fb2b70272b41de5b5df610c958.tar.gz bcm5719-llvm-f33d9052935869fb2b70272b41de5b5df610c958.zip | |
[X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)
Give the bit count instructions their own scheduler classes instead of forcing them into existing classes.
These were mostly overridden anyway, but I had to add in costs from Agner for silvermont and znver1 and the Fam16h SoG for btver2 (Jaguar).
Differential Revision: https://reviews.llvm.org/D44879
llvm-svn: 328566
Diffstat (limited to 'clang/lib/Sema/SemaTemplateInstantiateDecl.cpp')
0 files changed, 0 insertions, 0 deletions
