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| author | Evan Cheng <evan.cheng@apple.com> | 2012-02-23 01:19:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-02-23 01:19:06 +0000 |
| commit | e87681cf34fb9ca032f44047aa296b972d026eea (patch) | |
| tree | 341afe9d42c85b82ee24809c04b38192d60f458c /clang/lib/Sema/SemaDeclAttr.cpp | |
| parent | 38ce889cb61869bc4b1a2b4c57b899e5e642a496 (diff) | |
| download | bcm5719-llvm-e87681cf34fb9ca032f44047aa296b972d026eea.tar.gz bcm5719-llvm-e87681cf34fb9ca032f44047aa296b972d026eea.zip | |
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
llvm-svn: 151224
Diffstat (limited to 'clang/lib/Sema/SemaDeclAttr.cpp')
0 files changed, 0 insertions, 0 deletions
