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authorCraig Topper <craig.topper@intel.com>2017-09-05 19:09:02 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-05 19:09:02 +0000
commit784fa8a4e30a6a70a09a1d8008515b43e00104d7 (patch)
tree9f3152d2fd96c28426beb19db617cc3439c62d3b /clang/lib/Sema/SemaCoroutine.cpp
parent80528702c9f54212813231d80c63a9a599e40e60 (diff)
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[X86] Remove unnecessary (v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X)))) patterns
We had already disabled the pattern for SSE4.1 and SSE4.2. But it got re-enabled for AVX and AVX512. With SSE41 we rely on a separate (v4f32 (X86vzmovl VR128)) pattern to select blendps with a xorps to create zeroess. And a separate (v4f32 (scalar_to_vector FR32X)) to select a COPY_TO_REG_CLASS to move FR32 to VR128 The same thing can happen for AVX with vblendps and those separate patterns already exist. For AVX512, (v4f32 (X86vzmov VR128)) will select a VMOVSS instruction instead of VBLENDPS due to their not being a EVEX VBLENDPS. This is what we were getting out of the larger pattern anyway. So the larger pattern is unneeded for AVX512 too. For SSE1-SSSE3 we can rely on (v4f32 (X86vzmov VR128)) selecting a MOVSS similar to AVX512. Again this is what the larger pattern did too. So the only real change here is that AVX1/2 now properly outputs a VBLENDPS during isel instead of a VMOVSS to match SSE41. Most tests didn't notice because the two address instruction pass knows how to turn VMOVSS into VBLENDPS to get an independent destination register. llvm-svn: 312564
Diffstat (limited to 'clang/lib/Sema/SemaCoroutine.cpp')
0 files changed, 0 insertions, 0 deletions
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