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| author | Artem Tamazov <artem.tamazov@amd.com> | 2016-05-27 12:50:13 +0000 |
|---|---|---|
| committer | Artem Tamazov <artem.tamazov@amd.com> | 2016-05-27 12:50:13 +0000 |
| commit | 7da9b82e0287704468ca79f3357d1723dbf5ce00 (patch) | |
| tree | 91762f7b75b00e6c10448001d8fa0c38fcbc6227 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | bc90075629625ae888ed6b08859509f884b997fa (diff) | |
| download | bcm5719-llvm-7da9b82e0287704468ca79f3357d1723dbf5ce00.tar.gz bcm5719-llvm-7da9b82e0287704468ca79f3357d1723dbf5ce00.zip | |
[AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional.
Register numbers may be specified as assembly-time expressions.
This feature can be useful in macros and alike. However, expressions
are supported within sqare braces only.
Sqare braces were initially intended to support specifying of multiple
(pairs/quads...) registers. Syntax like v[8:8] which specifies single register
is also supported. That allows expressions but looks a bit unnatural.
This change supports syntax REG[EXPR].
Tests added.
Differential Revision: http://reviews.llvm.org/D20588
llvm-svn: 270990
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions
