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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2016-10-31 18:59:52 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2016-10-31 18:59:52 +0000
commit75cda2f2b50f7872e129f700663251711a3a2923 (patch)
tree353da5e629f2bdda9b920dd8a6ada51912361b74 /clang/lib/Frontend/CompilerInvocation.cpp
parent63b4a37ef56e21490dfb0bc4148f992f713f87cb (diff)
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Fix per-processor model scheduler definition completeness check
The CodeGenSchedModels::checkCompleteness routine in TableGen/ CodeGenSchedule.cpp is supposed to verify for each processor model that is marked as "complete" that it actually defines a scheduling class for each instruction. However, this did not work correctly due to an incorrect check whether a scheduling class has an itinerary. Reviewer: atrick Differential revision: https://reviews.llvm.org/D26156 llvm-svn: 285622
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