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author | Sanjay Patel <spatel@rotateright.com> | 2016-10-31 23:28:45 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-31 23:28:45 +0000 |
commit | 70c5f02d25d29b1330b2747352994812d802aeaf (patch) | |
tree | bc4bf70d880e7445e25b63443de1a654311bec45 /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | 525a3514479692be9704210f18f7ef9fa58758d9 (diff) | |
download | bcm5719-llvm-70c5f02d25d29b1330b2747352994812d802aeaf.tar.gz bcm5719-llvm-70c5f02d25d29b1330b2747352994812d802aeaf.zip |
[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841)
This bug was exposed by using nsw/nuw for more aggressive folds in:
https://reviews.llvm.org/rL284844
The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(),
but we can't just flip flag bits in the DAG; we have to create a new node that has the
bits cleared.
This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30841
llvm-svn: 285656
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions